[BULK] RE: [LinuxBIOS] FYI: AMD support for cache as ram.

yhlu yinghailu at gmail.com
Tue Jun 7 06:02:24 CEST 2005

I just figure out, the ss don't need to be changed. and only need to
set the esp.

It can get into amd64_main in failover.

the it seems even the 64 range in cache can be read and write, but the
result is not right. It means when clear all of range, the readout
will still be 0xff....

 #if 1
        movl    $CacheBase, %edi
        movl    $04000, %ecx
        xorl    %eax, %eax
        rep     stosl
        movl  $CacheBase, %esi
        movl (%esi), %eax
.testx:        outb %al, $0x80
         jmp .testx
        intel_chip_post_macro(0x22)     /* post 22 */
      are you sure that your code can use 300 bytes in cache?


More information about the coreboot mailing list