[BULK] RE: [LinuxBIOS] FYI: AMD support for cache as ram.

YhLu YhLu at tyan.com
Mon Jun 6 22:21:02 CEST 2005


I'm trying to enable the CAR for opteron.

1. create failover.inc and auto.inc with gcc -S
2. change the label in failover.inc from .L --> .fL
3. change section name in failover.inc and auto.c
	.text --> .rom.text
	.rodata--> .rom.data
	.rodata.str...-> .rom.data.str...
4. using following cache_as_ram.inc, and it will be executed after entry.inc
	at last it will call amd64 in failover.inc or auto.inc
5. current it will die after post code 0x22

I wonder how to make the cpu using the stack in cache....

        movl    $(CacheBase>>4), %eax
        movl    %eax, %ss

is enough?

Also how to using gcc parammetor to do 2, and 3....

YH

/* cache_as_ram.c */
#define CacheBase 0x60000

#include <cpu/x86/mtrr.h>
#include <cpu/amd/mtrr.h>

        /* Save the BIST result */
        movl    %eax, %ebp

CacheAsRam:

        xorl    %eax, %eax                      # clear %eax and %edx
        xorl    %edx, %edx                      #
        movl    $fixed_mtrr_msr, %esi

enable_fixed_mtrr_dram_modify:
        movl    $SYSCFG_MSR, %ecx
        rdmsr
        orl     $SYSCFG_MSR_MtrrFixDramModEn, %eax
        wrmsr

        /*Clear all MTRRs */
clear_fixed_var_mtrr:
        lodsl   (%esi), %eax
        testl   %eax, %eax
        jz      clear_fixed_var_mtrr_out
        
        movl    %eax, %ecx
        xorl    %eax, %eax
        wrmsr   
        
        jmp     clear_fixed_var_mtrr
clear_fixed_var_mtrr_out:

        /* enable mtrr dram enable */
enable_fixed_var_mtrr_dram:
        movl    $SYSCFG_MSR, %ecx
        rdmsr
        orl     $(7<<18), %eax
        wrmsr

        /* enable caching for 64K using variable mtrr */
        movl    $0x200, %ecx
        xorl    %edx, %edx
        movl     $(CacheBase | MTRR_TYPE_WRBACK), %eax
        wrmsr   

        movl    $0x201, %ecx
        movl    $0x000000ff, %edx # AMD 40 bit
        movl    $((~((CacheBase + 0x10000) - 1)) | 0x800), %eax
        wrmsr  

        /* make it to be IO by clearing RD Dram and WR Dram */
        movl    $IORR0_BASE, %ecx
        xorl    %edx, %edx
        movl    $CacheBase, %eax             # bit 3, and bit = 0 mean clear
RD ram and ER ram 
        wrmsr

        movl    $IORR0_MASK, %ecx
        movl    $0x000000ff, %edx
        movl    $(~((CacheBase + 0x10000) - 1) | 0x800), %eax
        wrmsr 

        /* enable cache */
        movl    %cr0, %eax
        andl    $0x9fffffff,%eax
        movl    %eax, %cr0

        intel_chip_post_macro(0x21)     /* post 21 */
#if 1
        /* we zerod it above */
        /* consistency: clear stack */
        movl    $(CacheBase+0x5000), %edi
        movl    $0x100, %ecx
        xorl    %eax, %eax
        rep     stosl
#endif

        intel_chip_post_macro(0x22)     /* post 22 */

//      movl    $(CacheBase+0x10000-4), %esp
        movl    $(CacheBase>>4), %eax
        movl    %eax, %ss

        /* Load a different set of data segments */
#if 0
        movw    $CACHE_RAM_DATA_SEG, %ax
        movw    %ax, %ds
        movw    %ax, %es
        movw    %ax, %ss
#endif

lout:
        /* Restore the BIST result */
        movl    %ebp, %eax
        jmp     _start_init

fixed_mtrr_msr: 
        .long   0x250, 0x258, 0x259
        .long   0x268, 0x269, 0x26A
        .long   0x26B, 0x26C, 0x26D
        .long   0x26E, 0x26F 
var_mtrr_msr:   
        .long   0x200, 0x201, 0x202, 0x203
        .long   0x204, 0x205, 0x206, 0x207
        .long   0x208, 0x209, 0x20A, 0x20B
        .long   0x20C, 0x20D, 0x20E, 0x20F
var_iorr_msr:
        .long   0xC0010016, 0xC0010017, 0xC0010018, 0xC0010019
mem_top:
        .long   0xC001001A, 0xC001001D
        .long   0x000 /* NULL, end of table */
_start_init:
        cli

        intel_chip_post_macro(0x23)     /* post 23 */
        call    amd64_main
        intel_chip_post_macro(0x24)     /* post 24 */ 





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