[LinuxBIOS] EPIA-M first round of patches.
Jonathan McDowell
noodles at earth.li
Thu Aug 4 19:36:35 CEST 2005
Attached are my first round of EPIA-M patches. They get it compiling to
the point of hitting the udelay patches and are basically what had been
committed to my arch tree.
01-epiam-config-fixup.diff
Fix up the config files so buildtarget runs
03-vt8235-fixup.diff
Fix up compilation of the VT8235 southbridge
04-epim-mainboard-config-fixup.diff
Fix up the mainboard config file for the southbridge devices
etc.
05-vt8623-fixup.diff
Fix up the VT8623 northbridge.
06-vt1211-fixup.diff
Fix up the VT1211 SuperIO device.
Comments appreciated; if I don't hear anything by the end of the weekend
I'll assume it's ok to commit.
J.
--
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diff -ruN LinuxBIOSv2.02/src/southbridge/via/vt8235/chip.h LinuxBIOSv2.03/src/southbridge/via/vt8235/chip.h
--- LinuxBIOSv2.02/src/southbridge/via/vt8235/chip.h 2005-08-03 15:12:36.955864000 +0100
+++ LinuxBIOSv2.03/src/southbridge/via/vt8235/chip.h 2005-08-03 16:23:51.843028500 +0100
@@ -1,7 +1,7 @@
#ifndef _SOUTHBRIDGE_VIA_VT8235
#define _SOUTHBRIDGE_VIA_VT8235
-extern struct chip_operations southbridge_via_vt8235_control;
+extern struct chip_operations southbridge_via_vt8235_ops;
struct southbridge_via_vt8235_config {
/* PCI function enables */
diff -ruN LinuxBIOSv2.02/src/southbridge/via/vt8235/Config.lb LinuxBIOSv2.03/src/southbridge/via/vt8235/Config.lb
--- LinuxBIOSv2.02/src/southbridge/via/vt8235/Config.lb 2005-08-03 15:12:36.951864000 +0100
+++ LinuxBIOSv2.03/src/southbridge/via/vt8235/Config.lb 2005-08-03 16:28:57.270116500 +0100
@@ -1,2 +1,6 @@
config chip.h
-object vt8235.o
+driver vt8235.o
+driver vt8235_ide.o
+driver vt8235_lpc.o
+driver vt8235_nic.o
+driver vt8235_usb.o
diff -ruN LinuxBIOSv2.02/src/southbridge/via/vt8235/vt8235.c LinuxBIOSv2.03/src/southbridge/via/vt8235/vt8235.c
--- LinuxBIOSv2.02/src/southbridge/via/vt8235/vt8235.c 2005-08-03 15:12:36.979866000 +0100
+++ LinuxBIOSv2.03/src/southbridge/via/vt8235/vt8235.c 2005-08-03 16:29:02.786461250 +0100
@@ -1,267 +1,36 @@
-
-#include <arch/io.h>
+#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
-#include <console/console.h>
+#include <pc80/keyboard.h>
#include "vt8235.h"
#include "chip.h"
-void rtc_init(int i);
-
-void pc_keyboard_init(void);
+/*
+ * Base VT8235.
+ */
+static device_t lpc_dev;
void hard_reset(void)
{
printk_err("NO HARD RESET ON VT8235! FIX ME!\n");
}
-static void usb_on(int enable)
-{
- unsigned char regval;
-
- /* Base 8235 controller */
- device_t dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, 0);
- /* USB controller 1 */
- device_t dev1 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, 0);
- /* USB controller 2 */
- device_t dev2 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, dev1);
- /* USB controller 2 */
- device_t dev3 = dev_find_device(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_82C586_2, dev2);
-
- if(enable){
- if(dev0) {
- regval = pci_read_config8(dev0, 0x50);
- regval &= ~(0x36);
- pci_write_config8(dev0, 0x50, regval);
- }
-
- /* enable USB1 */
- if(dev1) {
- pci_write_config8(dev1, 0x04, 0x07);
- }
-
- /* enable USB2 */
- if(dev2) {
- pci_write_config8(dev2, 0x04, 0x07);
- }
-
- /* enable USB3 */
- if(dev3) {
- pci_write_config8(dev3, 0x04, 0x07);
- }
-
- }else{
- if(dev0) {
- regval = pci_read_config8(dev0, 0x50);
- regval |= 0x36;
- pci_write_config8(dev0, 0x50, regval);
- }
-
- /* disable USB1 */
- if(dev1) {
- pci_write_config8(dev1, 0x3c, 0x00);
- pci_write_config8(dev1, 0x04, 0x00);
- }
-
- /* disable USB2 */
- if(dev2) {
- pci_write_config8(dev2, 0x3c, 0x00);
- pci_write_config8(dev2, 0x04, 0x00);
- }
-
- /* disable USB3 */
- if(dev3) {
- pci_write_config8(dev3, 0x3c, 0x00);
- pci_write_config8(dev3, 0x04, 0x00);
- }
- }
-}
-
-static void keyboard_on(void)
+static void keyboard_on(struct device *dev)
{
unsigned char regval;
- /* Base 8235 controller */
- device_t dev0 = dev_find_device(PCI_VENDOR_ID_VIA, \
- PCI_DEVICE_ID_VIA_8235, 0);
+ regval = pci_read_config8(dev, 0x51);
+// regval |= 0x0f;
+ /* !!!FIX let's try this */
+ regval |= 0x1d;
+ pci_write_config8(dev, 0x51, regval);
- if (dev0) {
- regval = pci_read_config8(dev0, 0x51);
-// regval |= 0x0f;
- /* !!!FIX let's try this */
- regval |= 0x1d;
- pci_write_config8(dev0, 0x51, regval);
- }
- pc_keyboard_init();
+ init_pc_keyboard(0x60, 0x64, 0);
}
-static void nvram_on(void)
-{
- /*
- * the VIA 8235 South has a very different nvram setup than the
- * piix4e ...
- * turn on ProMedia nvram.
- * TO DO: use the PciWriteByte function here.
- */
-
- /*
- * kevinh/Ispiri - I don't think this is the correct address/value
- * intel_conf_writeb(0x80008841, 0xFF);
- */
-}
-
-
-/*
- * Enable the ethernet device and turn off stepping (because it is integrated
- * inside the southbridge)
- */
-static void ethernet_fixup()
-{
- device_t edev;
- uint8_t byte;
-
- printk_info("Ethernet fixup\n");
-
- edev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_7, 0);
- if (edev) {
- printk_debug("Configuring VIA LAN\n");
-
- /* We don't need stepping - though the device supports it */
- byte = pci_read_config8(edev, PCI_COMMAND);
- byte &= ~PCI_COMMAND_WAIT;
- pci_write_config8(edev, PCI_COMMAND, byte);
- } else {
- printk_debug("VIA LAN not found\n");
- }
-}
-
-
-/* we need to do things in this function so that PCI scan will find
- * them. One problem here is that we can't use ANY of the new device
- * stuff. This work here precedes all that.
- * Fundamental problem with linuxbios V2 architecture.
- * You can't do pci control in the C code without having done a PCI scan.
- * But in some cases you need to to pci control in the c code before doing
- * a PCI scan. But you can't use arch/romcc_io.h (the code you need) because
- * that has functions with the same name but different type signatures
- * (e.g. device_t). This needs to get fixed. We need low-level pci scans
- * in the C code.
- */
-static void vt8235_pci_enable(struct southbridge_via_vt8235_config *conf)
-{
- /*
- unsigned long busdevfn = 0x8000;
- if (conf->enable_ide) {
- printk_debug("%s: enabling IDE function\n", __FUNCTION__);
- }
- */
-}
-
-/* PIRQ init
- */
-void pci_assign_irqs(unsigned bus, unsigned slot, const unsigned char pIntAtoD[4]);
-
-/* taken some liberties - changed irq structures to pins numbers so that it is easier to
- * change PCI irq assignments without having to change each PCI function individually
- */
-
-/* pciIrqs contains the irqs assigned for PCI pins A-D */
-/* setting will depend on motherboard as irqs can be quite scarce */
-/* e.g on EPIA-MII, 16 bit CF card wants a dedicated IRQ. A 16 bit card in pcmcia socket */
-/* may want another - for now only claim 3 interupts for PCI, leaving at least one spare */
-/* for CF. */
-/* On EPIA-M one could allocated all four irqs to different numbers since there are no cardbus */
-/* devices */
-
-
-static const unsigned char pciIrqs[4] = { 5 , 9 , 9, 10 };
-
-static const unsigned char usbPins[4] = { 'A','B','C','D'};
-static const unsigned char enetPins[4] = { 'A','B','C','D'};
-static const unsigned char slotPins[4] = { 'B','C','D','A'};
-static const unsigned char firewirePins[4] = { 'B','C','D','A'};
-static const unsigned char vt8235Pins[4] = { 'A','B','C','D'};
-static const unsigned char vgaPins[4] = { 'A','B','C','D'};
-static const unsigned char cbPins[4] = { 'A','B','C','D'};
-static const unsigned char riserPins[4] = { 'A','B','C','D'};
-/*
- Our IDSEL mappings are as follows
- PCI slot is AD31 (device 15) (00:14.0)
- Southbridge is AD28 (device 12) (00:11.0)
-*/
-static unsigned char *pin_to_irq(const unsigned char *pin)
-{
- static unsigned char Irqs[4];
- int i;
- for (i = 0 ; i < 4 ; i++)
- Irqs[i] = pciIrqs[ pin[i] - 'A' ];
-
- return Irqs;
-}
-static void pci_routing_fixup(void)
-{
- device_t dev;
-
- dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, 0);
- printk_info("%s: dev is %p\n", __FUNCTION__, dev);
- if (dev) {
- /* initialize PCI interupts - these assignments depend
- on the PCB routing of PINTA-D
-
- PINTA = IRQ11
- PINTB = IRQ5
- PINTC = IRQ10
- PINTD = IRQ12
- */
- pci_write_config8(dev, 0x55, pciIrqs[0] << 4);
- pci_write_config8(dev, 0x56, pciIrqs[1] | (pciIrqs[2] << 4) );
- pci_write_config8(dev, 0x57, pciIrqs[3] << 4);
-
- }
-
-
-
- // firewire built into southbridge
- printk_info("setting firewire\n");
- pci_assign_irqs(0, 0x0d, pin_to_irq(firewirePins) );
-
- // Standard usb components
- printk_info("setting usb\n");
- pci_assign_irqs(0, 0x10, pin_to_irq(usbPins) );
-
- // VT8235 + sound hardware
- printk_info("setting vt8235\n");
- pci_assign_irqs(0, 0x11, pin_to_irq(vt8235Pins) );
-
- // Ethernet built into southbridge
- printk_info("setting ethernet\n");
- pci_assign_irqs(0, 0x12, pin_to_irq(enetPins) );
-
- // VGA
- printk_info("setting vga\n");
- pci_assign_irqs(1, 0x00, pin_to_irq(vgaPins) );
-
- // PCI slot
- printk_info("setting pci slot\n");
- pci_assign_irqs(0, 0x14, pin_to_irq(slotPins) );
-
- // Cardbus slot
- printk_info("setting cardbus slot\n");
- pci_assign_irqs(0, 0x0a, pin_to_irq(cbPins) );
-
- // Via 2 slot riser card 2nd slot
- printk_info("setting riser slot\n");
- pci_assign_irqs(0, 0x13, pin_to_irq(riserPins) );
-
-
-}
-
-
-void
-dump_south(void)
+void dump_south(void)
{
device_t dev0;
dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, 0);
@@ -276,288 +45,26 @@
}
}
-void set_led(void)
+void set_led(struct device *dev)
{
-
// set power led to steady now that lxbios has virtually done its job
- device_t dev0;
- dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235,0);
-
- pci_write_config8(dev0,0x94,0xb0);
-
-}
-
-/* set up the power management capabilities directly into ACPI mode */
-/* this avoids having to handle any System Management Interrupts (SMI's) which I can't */
-/* figure out how to do !!!! */
-
-void setup_pm(device_t dev0)
-{
-
- // Set gen config 0
- pci_write_config8(dev0,0x80,0x20);
-
- // Set ACPI base address to IO 0x4000
- pci_write_config16(dev0, 0x88, 0x0401);
-
- // set ACPI irq to 5
- pci_write_config8(dev0,0x82,0x55);
-
- // primary interupt channel
- pci_write_config16(dev0,0x84,0x30f2);
-
- // throttle / stop clock control
- pci_write_config8(dev0,0x8d,0x18);
-
- pci_write_config8(dev0,0x93,0x88);
- //pci_write_config8(dev0,0x94,0xb0);
- pci_write_config8(dev0,0x95,0xc0);
- pci_write_config8(dev0,0x98,0);
- pci_write_config8(dev0,0x99,0xea);
- pci_write_config8(dev0,0xe4,0x14);
- pci_write_config8(dev0,0xe5,0x08);
-
-
- // Enable ACPI access (and setup like award)
- pci_write_config8(dev0, 0x81, 0x84);
-
- outw(0xffff,0x400);
- outw(0xffff,0x420);
- outw(0xffff,0x428);
- outl(0xffffffff,0x430);
-
- outw(0x0,0x424);
- outw(0x0,0x42a);
- outw(0x1,0x42c);
- outl(0x0,0x434);
- outl(0x01,0x438);
- outb(0x0,0x442);
- outl(0xffff7fff,0x448);
- outw(0x001,0x404);
-
-
-}
-
-static void vt8235_init(struct southbridge_via_vt8235_config *conf)
-{
- unsigned char enables;
- device_t dev0;
- device_t dev1;
- //device_t devpwr;
- //int i;
-
- // to do: use the pcibios_find function here, instead of
- // hard coding the devfn.
- // done - kevinh/Ispiri
- printk_debug("vt8235 init\n");
- /* Base 8235 controller */
- dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, 0);
- /* IDE controller */
- dev1 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, 0);
- /* Power management controller */
- //devpwr = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_4, 0);
-
- // enable the internal I/O decode
- enables = pci_read_config8(dev0, 0x6C);
- enables |= 0x80;
- pci_write_config8(dev0, 0x6C, enables);
-
- // Map 4MB of FLASH into the address space
- pci_write_config8(dev0, 0x41, 0x7f);
-
- // Set bit 6 of 0x40, because Award does it (IO recovery time)
- // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
- // interrupts can be properly marked as level triggered.
- enables = pci_read_config8(dev0, 0x40);
- enables |= 0x45;
- pci_write_config8(dev0, 0x40, enables);
-
- // Set 0x42 to 0xf0 to match Award bios
- enables = pci_read_config8(dev0, 0x42);
- enables |= 0xf0;
- pci_write_config8(dev0, 0x42, enables);
-
-
- /* Set 0x58 to 0x03 to match Award */
- pci_write_config8(dev0, 0x58, 0x03);
-
- /* Set bit 3 of 0x4f to match award (use INIT# as cpu reset) */
- enables = pci_read_config8(dev0, 0x4f);
- enables |= 0x08;
- pci_write_config8(dev0, 0x4f, enables);
-
-
-
- // Set bit 3 of 0x4a, to match award (dummy pci request)
- enables = pci_read_config8(dev0, 0x4a);
- enables |= 0x08;
- pci_write_config8(dev0, 0x4a, enables);
-
- // Set bit 3 of 0x4f to match award (use INIT# as cpu reset)
- enables = pci_read_config8(dev0, 0x4f);
- enables |= 0x08;
- pci_write_config8(dev0, 0x4f, enables);
-
- // Set 0x58 to 0x03 to match Award
- pci_write_config8(dev0, 0x58, 0x03);
-
- // enable the ethernet/RTC
- if(dev0) {
- enables = pci_read_config8(dev0, 0x51);
- enables |= 0x18;
- pci_write_config8(dev0, 0x51, enables);
- }
-
-
- /* enable serial irq */
- pci_write_config8(dev0,0x52,0x9);
-
- /* dma */
- pci_write_config8(dev0, 0x53, 0x00);
-
- /* Use compatability mode - per award bios */
- pci_write_config32(dev1, 0x10, 0x0);
- pci_write_config32(dev1, 0x14, 0x0);
- pci_write_config32(dev1, 0x18, 0x0);
- pci_write_config32(dev1, 0x1c, 0x0);
-
-
- // Power management setup
- setup_pm(dev0);
-
- //
- //
- // IDE setup
- //
- if (! conf->enable_native_ide) {
- // Run the IDE controller in 'compatiblity mode - i.e. don't use PCI
- // interrupts. Using PCI ints confuses linux for some reason.
-
- printk_info("%s: enabling compatibility IDE addresses\n", __FUNCTION__);
- enables = pci_read_config8(dev1, 0x42);
- printk_debug("enables in reg 0x42 0x%x\n", enables);
- enables &= ~0xc0; // compatability mode
- pci_write_config8(dev1, 0x42, enables);
- enables = pci_read_config8(dev1, 0x42);
- printk_debug("enables in reg 0x42 read back as 0x%x\n", enables);
- }
-
- enables = pci_read_config8(dev1, 0x40);
- printk_debug("enables in reg 0x40 0x%x\n", enables);
- enables |= 3;
- pci_write_config8(dev1, 0x40, enables);
- enables = pci_read_config8(dev1, 0x40);
- printk_debug("enables in reg 0x40 read back as 0x%x\n", enables);
-
- // Enable prefetch buffers
- enables = pci_read_config8(dev1, 0x41);
- enables |= 0xf0;
- pci_write_config8(dev1, 0x41, enables);
-
- // Lower thresholds (cause award does it)
- enables = pci_read_config8(dev1, 0x43);
- enables &= ~0x0f;
- enables |= 0x05;
- pci_write_config8(dev1, 0x43, enables);
-
- // PIO read prefetch counter (cause award does it)
- pci_write_config8(dev1, 0x44, 0x18);
-
- // Use memory read multiple
- pci_write_config8(dev1, 0x45, 0x1c);
-
- // address decoding.
- // we want "flexible", i.e. 1f0-1f7 etc. or native PCI
- // kevinh at ispiri.com - the standard linux drivers seem ass slow when
- // used in native mode - I've changed back to classic
- enables = pci_read_config8(dev1, 0x9);
- printk_debug("enables in reg 0x9 0x%x\n", enables);
- // by the book, set the low-order nibble to 0xa.
- if (conf->enable_native_ide) {
- enables &= ~0xf;
- // cf/cg silicon needs an 'f' here.
- enables |= 0xf;
- } else {
- enables &= ~0x5;
- }
-
- pci_write_config8(dev1, 0x9, enables);
- enables = pci_read_config8(dev1, 0x9);
- printk_debug("enables in reg 0x9 read back as 0x%x\n", enables);
-
- // standard bios sets master bit.
- enables = pci_read_config8(dev1, 0x4);
- printk_debug("command in reg 0x4 0x%x\n", enables);
- enables |= 7;
-
- // No need for stepping - kevinh at ispiri.com
- enables &= ~0x80;
-
- pci_write_config8(dev1, 0x4, enables);
- enables = pci_read_config8(dev1, 0x4);
- printk_debug("command in reg 0x4 reads back as 0x%x\n", enables);
-
- if (! conf->enable_native_ide) {
- // Use compatability mode - per award bios
- pci_write_config32(dev1, 0x10, 0x0);
- pci_write_config32(dev1, 0x14, 0x0);
- pci_write_config32(dev1, 0x18, 0x0);
- pci_write_config32(dev1, 0x1c, 0x0);
-
- // Force interrupts to use compat mode - just like Award bios
- pci_write_config8(dev1, 0x3d, 00);
- pci_write_config8(dev1, 0x3c, 0xff);
- }
-
-
- /* set up isa bus -- i/o recovery time, rom write enable, extend-ale */
- pci_write_config8(dev0, 0x40, 0x54);
- ethernet_fixup();
-
- // Start the rtc
- rtc_init(0);
-
-
+ pci_write_config8(dev, 0x94, 0xb0);
}
-static void southbridge_init(struct chip *chip, enum chip_pass pass)
+static void vt8235_enable(struct device *dev)
{
+ struct southbridge_via_vt8235_config *conf = dev->chip_info;
- struct southbridge_via_vt8235_config *conf =
- (struct southbridge_via_vt8235_config *)chip->chip_info;
-
- switch (pass) {
- case CONF_PASS_PRE_PCI:
- vt8235_pci_enable(conf);
- break;
-
- case CONF_PASS_POST_PCI:
- /* initialise the PIC - particularly so that VGA bios init code
- doesn't get nasty unknown interupt vectors when it tries to establish
- its interrupts. */
- setup_i8259();
- vt8235_init(conf);
- pci_routing_fixup();
- usb_on(1);
- keyboard_on();
- vga_fixup();
-
-
-
- break;
-
- case CONF_PASS_PRE_BOOT:
- dump_south();
- set_led();
- break;
-
- default:
- /* nothing yet */
- break;
+ printk_debug("In vt8235_enable.\n");
+ if (!lpc_dev) {
+ lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_8235, 0);
+ if (conf->enable_keyboard)
+ keyboard_on(lpc_dev);
}
}
-struct chip_operations southbridge_via_vt8235_control = {
+struct chip_operations southbridge_via_vt8235_ops = {
CHIP_NAME("VIA vt8235")
- .enable = southbridge_init,
+ .enable_dev = vt8235_enable,
};
diff -ruN LinuxBIOSv2.02/src/southbridge/via/vt8235/vt8235_ide.c LinuxBIOSv2.03/src/southbridge/via/vt8235/vt8235_ide.c
--- LinuxBIOSv2.02/src/southbridge/via/vt8235/vt8235_ide.c 1970-01-01 01:00:00.000000000 +0100
+++ LinuxBIOSv2.03/src/southbridge/via/vt8235/vt8235_ide.c 2005-08-03 16:29:17.171360250 +0100
@@ -0,0 +1,114 @@
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ops.h>
+#include <device/pci_ids.h>
+#include <console/console.h>
+#include "vt8235.h"
+#include "chip.h"
+
+static void ide_init(struct device *dev)
+{
+ struct southbridge_via_vt8235_config *conf = dev->chip_info;
+ unsigned char enables;
+
+ printk_info("Enabling VIA IDE.\n");
+
+ if (!conf->enable_native_ide) {
+ /*
+ * Run the IDE controller in 'compatiblity mode - i.e. don't
+ * use PCI interrupts. Using PCI ints confuses linux for some
+ * reason.
+ */
+ printk_info("%s: enabling compatibility IDE addresses\n",
+ __FUNCTION__);
+ enables = pci_read_config8(dev, 0x42);
+ printk_debug("enables in reg 0x42 0x%x\n", enables);
+ enables &= ~0xc0; // compatability mode
+ pci_write_config8(dev, 0x42, enables);
+ enables = pci_read_config8(dev, 0x42);
+ printk_debug("enables in reg 0x42 read back as 0x%x\n",
+ enables);
+ }
+
+ enables = pci_read_config8(dev, 0x40);
+ printk_debug("enables in reg 0x40 0x%x\n", enables);
+ enables |= 3;
+ pci_write_config8(dev, 0x40, enables);
+ enables = pci_read_config8(dev, 0x40);
+ printk_debug("enables in reg 0x40 read back as 0x%x\n", enables);
+
+ // Enable prefetch buffers
+ enables = pci_read_config8(dev, 0x41);
+ enables |= 0xf0;
+ pci_write_config8(dev, 0x41, enables);
+
+ // Lower thresholds (cause award does it)
+ enables = pci_read_config8(dev, 0x43);
+ enables &= ~0x0f;
+ enables |= 0x05;
+ pci_write_config8(dev, 0x43, enables);
+
+ // PIO read prefetch counter (cause award does it)
+ pci_write_config8(dev, 0x44, 0x18);
+
+ // Use memory read multiple
+ pci_write_config8(dev, 0x45, 0x1c);
+
+ // address decoding.
+ // we want "flexible", i.e. 1f0-1f7 etc. or native PCI
+ // kevinh at ispiri.com - the standard linux drivers seem ass slow when
+ // used in native mode - I've changed back to classic
+ enables = pci_read_config8(dev, 0x9);
+ printk_debug("enables in reg 0x9 0x%x\n", enables);
+ // by the book, set the low-order nibble to 0xa.
+ if (conf->enable_native_ide) {
+ enables &= ~0xf;
+ // cf/cg silicon needs an 'f' here.
+ enables |= 0xf;
+ } else {
+ enables &= ~0x5;
+ }
+
+ pci_write_config8(dev, 0x9, enables);
+ enables = pci_read_config8(dev, 0x9);
+ printk_debug("enables in reg 0x9 read back as 0x%x\n", enables);
+
+ // standard bios sets master bit.
+ enables = pci_read_config8(dev, 0x4);
+ printk_debug("command in reg 0x4 0x%x\n", enables);
+ enables |= 7;
+
+ // No need for stepping - kevinh at ispiri.com
+ enables &= ~0x80;
+
+ pci_write_config8(dev, 0x4, enables);
+ enables = pci_read_config8(dev, 0x4);
+ printk_debug("command in reg 0x4 reads back as 0x%x\n", enables);
+
+ if (!conf->enable_native_ide) {
+ // Use compatability mode - per award bios
+ pci_write_config32(dev, 0x10, 0x0);
+ pci_write_config32(dev, 0x14, 0x0);
+ pci_write_config32(dev, 0x18, 0x0);
+ pci_write_config32(dev, 0x1c, 0x0);
+
+ // Force interrupts to use compat mode - just like Award bios
+ pci_write_config8(dev, 0x3d, 0x0);
+ pci_write_config8(dev, 0x3c, 0xff);
+ }
+}
+
+static struct device_operations ide_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = ide_init,
+ .enable = 0,
+ .ops_pci = 0,
+};
+
+static struct pci_driver northbridge_driver __pci_driver = {
+ .ops = &ide_ops,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_82C586_1,
+};
diff -ruN LinuxBIOSv2.02/src/southbridge/via/vt8235/vt8235_lpc.c LinuxBIOSv2.03/src/southbridge/via/vt8235/vt8235_lpc.c
--- LinuxBIOSv2.02/src/southbridge/via/vt8235/vt8235_lpc.c 1970-01-01 01:00:00.000000000 +0100
+++ LinuxBIOSv2.03/src/southbridge/via/vt8235/vt8235_lpc.c 2005-08-03 16:29:26.003912250 +0100
@@ -0,0 +1,245 @@
+#include <arch/io.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ops.h>
+#include <device/pci_ids.h>
+
+#include <pc80/mc146818rtc.h>
+
+#include "vt8235.h"
+#include "chip.h"
+
+/*
+ * Taken some liberties - changed irq structures to pins numbers so that it is
+ * easier to change PCI irq assignments without having to change each PCI
+ * function individually
+ *
+ * pciIrqs contains the irqs assigned for PCI pins A-D
+ *
+ * Setting will depend on motherboard as irqs can be quite scarce e.g on
+ * EPIA-MII, 16 bit CF card wants a dedicated IRQ. A 16 bit card in pcmcia
+ * socket may want another - for now only claim 3 interupts for PCI, leaving at
+ * least one spare for CF. On EPIA-M one could allocated all four irqs to
+ * different numbers since there are no cardbus devices
+ */
+
+static const unsigned char pciIrqs[4] = { 11 , 5, 10 , 12 };
+
+static const unsigned char usbPins[4] = { 'A','B','C','D'};
+static const unsigned char enetPins[4] = { 'A','B','C','D'};
+static const unsigned char slotPins[4] = { 'B','C','D','A'};
+static const unsigned char firewirePins[4] = { 'B','C','D','A'};
+static const unsigned char vt8235Pins[4] = { 'A','B','C','D'};
+static const unsigned char vgaPins[4] = { 'A','B','C','D'};
+static const unsigned char cbPins[4] = { 'A','B','C','D'};
+static const unsigned char riserPins[4] = { 'A','B','C','D'};
+
+/*
+ Our IDSEL mappings are as follows
+ PCI slot is AD31 (device 15) (00:14.0)
+ Southbridge is AD28 (device 12) (00:11.0)
+*/
+
+static unsigned char *pin_to_irq(const unsigned char *pin)
+{
+ static unsigned char Irqs[4];
+ int i;
+ for (i = 0 ; i < 4 ; i++)
+ Irqs[i] = pciIrqs[ pin[i] - 'A' ];
+
+ return Irqs;
+}
+
+static void pci_routing_fixup(struct device *dev)
+{
+ printk_info("%s: dev is %p\n", __FUNCTION__, dev);
+ if (dev) {
+ /* initialize PCI interupts - these assignments depend
+ on the PCB routing of PINTA-D
+
+ PINTA = IRQ11
+ PINTB = IRQ5
+ PINTC = IRQ10
+ PINTD = IRQ12
+ */
+ pci_write_config8(dev, 0x55, pciIrqs[0] << 4);
+ pci_write_config8(dev, 0x56, pciIrqs[1] | (pciIrqs[2] << 4) );
+ pci_write_config8(dev, 0x57, pciIrqs[3] << 4);
+ }
+
+ // firewire built into southbridge
+ printk_info("setting firewire\n");
+ pci_assign_irqs(0, 0x0d, pin_to_irq(firewirePins));
+
+ // Standard usb components
+ printk_info("setting usb\n");
+ pci_assign_irqs(0, 0x10, pin_to_irq(usbPins));
+
+ // VT8235 + sound hardware
+ printk_info("setting vt8235\n");
+ pci_assign_irqs(0, 0x11, pin_to_irq(vt8235Pins));
+
+ // Ethernet built into southbridge
+ printk_info("setting ethernet\n");
+ pci_assign_irqs(0, 0x12, pin_to_irq(enetPins));
+
+ // VGA
+ printk_info("setting vga\n");
+ pci_assign_irqs(1, 0x00, pin_to_irq(vgaPins));
+
+ // PCI slot
+ printk_info("setting pci slot\n");
+ pci_assign_irqs(0, 0x14, pin_to_irq(slotPins));
+
+ // Cardbus slot
+ printk_info("setting cardbus slot\n");
+ pci_assign_irqs(0, 0x0a, pin_to_irq(cbPins));
+
+ // Via 2 slot riser card 2nd slot
+ printk_info("setting riser slot\n");
+ pci_assign_irqs(0, 0x13, pin_to_irq(riserPins));
+
+ printk_spew("%s: DONE\n", __FUNCTION__);
+}
+
+/*
+ * Set up the power management capabilities directly into ACPI mode. This
+ * avoids having to handle any System Management Interrupts (SMI's) which I
+ * can't figure out how to do !!!!
+ */
+
+void setup_pm(device_t dev)
+{
+
+ // Set gen config 0
+ pci_write_config8(dev, 0x80, 0x20);
+
+ // Set ACPI base address to IO 0x4000
+ pci_write_config16(dev, 0x88, 0x0401);
+
+ // set ACPI irq to 5
+ pci_write_config8(dev, 0x82, 0x45);
+
+ // primary interupt channel
+ pci_write_config16(dev, 0x84, 0x30f2);
+
+ // throttle / stop clock control
+ pci_write_config8(dev, 0x8d, 0x18);
+
+ pci_write_config8(dev, 0x93, 0x88);
+ pci_write_config8(dev, 0x94, 0xb0);
+ pci_write_config8(dev, 0x95, 0xc0);
+ pci_write_config8(dev, 0x98, 0);
+ pci_write_config8(dev, 0x99, 0xea);
+ pci_write_config8(dev, 0xe4, 0x14);
+ pci_write_config8(dev, 0xe5, 0x08);
+
+
+ // Enable ACPI access (and setup like award)
+ pci_write_config8(dev, 0x81, 0x84);
+
+ outw(0xffff, 0x400);
+ outw(0xffff, 0x420);
+ outw(0xffff, 0x428);
+ outl(0xffffffff, 0x430);
+
+ outw(0x0, 0x424);
+ outw(0x0, 0x42a);
+ outw(0x1, 0x42c);
+ outl(0x0, 0x434);
+ outl(0x01, 0x438);
+ outb(0x0, 0x442);
+ outl(0xffff7fff, 0x448);
+ outw(0x001, 0x404);
+}
+
+static void vt8235_init(struct device *dev)
+{
+ unsigned char enables;
+
+ printk_debug("vt8235 init\n");
+
+ // enable the internal I/O decode
+ enables = pci_read_config8(dev, 0x6C);
+ enables |= 0x80;
+ pci_write_config8(dev, 0x6C, enables);
+
+ // Map 4MB of FLASH into the address space
+ pci_write_config8(dev, 0x41, 0x7f);
+
+ // Set bit 6 of 0x40, because Award does it (IO recovery time)
+ // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
+ // interrupts can be properly marked as level triggered.
+ enables = pci_read_config8(dev, 0x40);
+ enables |= 0x45;
+ pci_write_config8(dev, 0x40, enables);
+
+ // Set 0x42 to 0xf0 to match Award bios
+ enables = pci_read_config8(dev, 0x42);
+ enables |= 0xf0;
+ pci_write_config8(dev, 0x42, enables);
+
+ /* Set 0x58 to 0x03 to match Award */
+ pci_write_config8(dev, 0x58, 0x03);
+
+ /* Set bit 3 of 0x4f to match award (use INIT# as cpu reset) */
+ enables = pci_read_config8(dev, 0x4f);
+ enables |= 0x08;
+ pci_write_config8(dev, 0x4f, enables);
+
+ // Set bit 3 of 0x4a, to match award (dummy pci request)
+ enables = pci_read_config8(dev, 0x4a);
+ enables |= 0x08;
+ pci_write_config8(dev, 0x4a, enables);
+
+ // Set bit 3 of 0x4f to match award (use INIT# as cpu reset)
+ enables = pci_read_config8(dev, 0x4f);
+ enables |= 0x08;
+ pci_write_config8(dev, 0x4f, enables);
+
+ // Set 0x58 to 0x03 to match Award
+ pci_write_config8(dev, 0x58, 0x03);
+
+ // enable the ethernet/RTC
+ if (dev) {
+ enables = pci_read_config8(dev, 0x51);
+ enables |= 0x18;
+ pci_write_config8(dev, 0x51, enables);
+ }
+
+ /* enable serial irq */
+ pci_write_config8(dev, 0x52, 0x9);
+
+ /* dma */
+ pci_write_config8(dev, 0x53, 0x00);
+
+ // Power management setup
+ setup_pm(dev);
+
+ /* set up isa bus -- i/o recovery time, rom write enable, extend-ale */
+ pci_write_config8(dev, 0x40, 0x54);
+
+ // Start the rtc
+ rtc_init(0);
+}
+
+static void southbridge_init(struct device *dev)
+{
+ vt8235_init(dev);
+ pci_routing_fixup(dev);
+}
+
+static struct device_operations vt8235_lpc_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = &southbridge_init,
+ .scan_bus = scan_static_bus,
+};
+
+static struct pci_driver lpc_driver __pci_driver = {
+ .ops = &vt8235_lpc_ops,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_8235,
+};
diff -ruN LinuxBIOSv2.02/src/southbridge/via/vt8235/vt8235_nic.c LinuxBIOSv2.03/src/southbridge/via/vt8235/vt8235_nic.c
--- LinuxBIOSv2.02/src/southbridge/via/vt8235/vt8235_nic.c 1970-01-01 01:00:00.000000000 +0100
+++ LinuxBIOSv2.03/src/southbridge/via/vt8235/vt8235_nic.c 2005-08-03 16:29:34.272429000 +0100
@@ -0,0 +1,37 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ops.h>
+#include <device/pci_ids.h>
+#include "vt8235.h"
+
+/*
+ * Enable the ethernet device and turn off stepping (because it is integrated
+ * inside the southbridge)
+ */
+static void nic_init(struct device *dev)
+{
+ uint8_t byte;
+
+ printk_debug("Configuring VIA Rhine LAN\n");
+
+ /* We don't need stepping - though the device supports it */
+ byte = pci_read_config8(dev, PCI_COMMAND);
+ byte &= ~PCI_COMMAND_WAIT;
+ pci_write_config8(dev, PCI_COMMAND, byte);
+}
+
+static struct device_operations nic_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = nic_init,
+ .enable = 0,
+ .ops_pci = 0,
+};
+
+static struct pci_driver northbridge_driver __pci_driver = {
+ .ops = &nic_ops,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_8233_7,
+};
diff -ruN LinuxBIOSv2.02/src/southbridge/via/vt8235/vt8235_usb.c LinuxBIOSv2.03/src/southbridge/via/vt8235/vt8235_usb.c
--- LinuxBIOSv2.02/src/southbridge/via/vt8235/vt8235_usb.c 1970-01-01 01:00:00.000000000 +0100
+++ LinuxBIOSv2.03/src/southbridge/via/vt8235/vt8235_usb.c 2005-08-03 16:29:40.604824750 +0100
@@ -0,0 +1,41 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ops.h>
+#include <device/pci_ids.h>
+#include "vt8235.h"
+
+static void usb_init(struct device *dev)
+{
+ printk_debug("Configuring VIA USB 1.1\n");
+
+ pci_write_config8(dev, 0x04, 0x07);
+
+ /*
+ * To disable; though do we need to do this?
+ pci_write_config8(dev1, 0x3c, 0x00);
+ pci_write_config8(dev1, 0x04, 0x00);
+
+ Also, on the root dev, for enable:
+ regval = pci_read_config8(dev0, 0x50);
+ regval &= ~(0x36);
+ pci_write_config8(dev0, 0x50, regval);
+
+ (regval |= 0x36; for disable)
+ */
+}
+
+static struct device_operations usb_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = usb_init,
+ .enable = 0,
+ .ops_pci = 0,
+};
+
+static struct pci_driver northbridge_driver __pci_driver = {
+ .ops = &usb_ops,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_82C586_2,
+};
-------------- next part --------------
diff -ruN LinuxBIOSv2.03/src/mainboard/via/epia-m/Config.lb LinuxBIOSv2.04/src/mainboard/via/epia-m/Config.lb
--- LinuxBIOSv2.03/src/mainboard/via/epia-m/Config.lb 2005-08-03 15:12:56.161065000 +0100
+++ LinuxBIOSv2.04/src/mainboard/via/epia-m/Config.lb 2005-08-03 16:35:39.375246500 +0100
@@ -138,8 +138,20 @@
register "enable_com_ports" = "1"
register "enable_keyboard" = "0"
register "enable_nvram" = "1"
- end
- chip southbridge/ricoh/rl5c476
+
+ device pci 10.0 on end # USB 1.1
+ device pci 10.1 on end # USB 1.1
+ device pci 10.2 on end # USB 1.1
+ device pci 10.3 on end # USB 2
+
+ device pci 11.0 on # Southbridge
+ end
+
+ device pci 11.1 on end # IDE
+ # 2-4 non existant?
+ device pci 11.5 on end # AC97 Audio
+ device pci 11.6 off end # AC97 Modem
+ device pci 12.0 on end # Ethernet
end
chip superio/via/vt1211
register "enable_com_ports" = "1"
@@ -147,7 +159,11 @@
register "enable_lpt" = "1"
register "enable_fdc" = "1"
end
- chip cpu/via/model_centaur
- end
+# This is on the EPIA MII, not the M.
+# chip southbridge/ricoh/rl5c476
+# end
+ end
+
+ chip cpu/via/model_centaur
end
end
-------------- next part --------------
diff -ruN LinuxBIOSv2.04/src/include/device/pci_ids.h LinuxBIOSv2.05/src/include/device/pci_ids.h
--- LinuxBIOSv2.04/src/include/device/pci_ids.h 2005-08-03 15:12:48.148564000 +0100
+++ LinuxBIOSv2.05/src/include/device/pci_ids.h 2005-08-03 18:01:46.534173750 +0100
@@ -1060,6 +1060,8 @@
#define PCI_DEVICE_ID_VIA_8233C_0 0x3109
#define PCI_DEVICE_ID_VIA_8361 0x3112
#define PCI_DEVICE_ID_VIA_8233A 0x3147
+#define PCI_DEVICE_ID_VIA_CLE266_VGA 0x3122
+#define PCI_DEVICE_ID_VIA_8623 0x3123
#define PCI_DEVICE_ID_VIA_86C100A 0x6100
#define PCI_DEVICE_ID_VIA_8231 0x8231
#define PCI_DEVICE_ID_VIA_8231_4 0x8235
diff -ruN LinuxBIOSv2.04/src/northbridge/via/vt8623/chip.h LinuxBIOSv2.05/src/northbridge/via/vt8623/chip.h
--- LinuxBIOSv2.04/src/northbridge/via/vt8623/chip.h 2005-08-03 15:13:16.862358000 +0100
+++ LinuxBIOSv2.05/src/northbridge/via/vt8623/chip.h 2005-08-03 16:38:42.298678500 +0100
@@ -2,4 +2,4 @@
{
};
-extern struct chip_operations northbridge_via_vt8623_control;
+extern struct chip_operations northbridge_via_vt8623_ops;
diff -ruN LinuxBIOSv2.04/src/northbridge/via/vt8623/northbridge.c LinuxBIOSv2.05/src/northbridge/via/vt8623/northbridge.c
--- LinuxBIOSv2.04/src/northbridge/via/vt8623/northbridge.c 2005-08-03 15:13:16.862358000 +0100
+++ LinuxBIOSv2.05/src/northbridge/via/vt8623/northbridge.c 2005-08-03 18:05:49.913384000 +0100
@@ -8,7 +8,8 @@
#include <stdlib.h>
#include <string.h>
#include <bitops.h>
-#include <cpu/p6/mtrr.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/mtrr.h>
#include "chip.h"
#include "northbridge.h"
@@ -18,7 +19,7 @@
* slower than normal, ethernet drops packets).
* Apparently these registers govern some sort of bus master behavior.
*/
-static void norhbrige_init(device_t dev)
+static void northbridge_init(device_t dev)
{
device_t fb_dev;
unsigned long fb;
@@ -60,15 +61,13 @@
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
- .init = northbridge_init,
- .scan_bus = pci_scan_bridge,
- .ops_pci = 0,
+ .init = northbridge_init
};
static struct pci_driver northbridge_driver __pci_driver = {
- .ops = &northbridge_ops,
+ .ops = &northbridge_operations,
.vendor = PCI_VENDOR_ID_VIA,
- .device = 0x3123,
+ .device = PCI_DEVICE_ID_VIA_8623,
};
static void agp_init(device_t dev)
@@ -93,23 +92,25 @@
};
static struct pci_driver agp_driver __pci_driver = {
- .ops = &agp_ops,
+ .ops = &agp_operations,
.vendor = PCI_VENDOR_ID_VIA,
- .device = 0xb091,
+ .device = PCI_DEVICE_ID_VIA_8633_1,
};
static void vga_init(device_t dev)
{
- unsigned long fb;
+// unsigned long fb;
printk_debug("VGA random fixup ...\n");
pci_write_config8(dev, 0x04, 0x07);
pci_write_config8(dev, 0x0d, 0x20);
- /* Set the vga mtrrs */
+ /* Set the vga mtrrs - disable for the moment */
+#if 0
add_var_mtrr( 0xd0000000 >> 10, 0x08000000>>10, MTRR_TYPE_WRCOMB);
fb = pci_read_config32(dev,0x10); // get the fb address
add_var_mtrr( fb>>10, 8192, MTRR_TYPE_WRCOMB);
+#endif
}
static struct device_operations vga_operations = {
@@ -121,7 +122,7 @@
};
static struct pci_driver vga_driver __pci_driver = {
- .ops = &vga_ops,
+ .ops = &vga_operations,
.vendor = PCI_VENDOR_ID_VIA,
.device = 0x3122,
};
@@ -132,17 +133,22 @@
static void pci_domain_read_resources(device_t dev)
{
struct resource *resource;
- unsigned reg;
+
+ printk_spew("Entering vt8623 pci_domain_read_resources.\n");
/* Initialize the system wide io space constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
resource->limit = 0xffffUL;
- resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+ resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+ IORESOURCE_ASSIGNED;
/* Initialize the system wide memory resources constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
resource->limit = 0xffffffffULL;
- resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+ resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+ IORESOURCE_ASSIGNED;
+
+ printk_spew("Leaving vt8623 pci_domain_read_resources.\n");
}
static void ram_resource(device_t dev, unsigned long index,
@@ -187,10 +193,11 @@
static void pci_domain_set_resources(device_t dev)
{
static const uint8_t ramregs[] = {0x5a, 0x5b, 0x5c, 0x5d };
- struct resource *resource, *last;
device_t mc_dev;
uint32_t pci_tolm;
+ printk_spew("Entering vt8623 pci_domain_set_resources.\n");
+
pci_tolm = find_pci_tolm(&dev->link[0]);
mc_dev = dev->link[0].children;
if (mc_dev) {
@@ -214,7 +221,7 @@
ramregs[i]);
}
printk_debug("I would set ram size to 0x%x Kbytes\n", (rambits)*16*1024);
- tomk = ramreg*16*1024 - 32768;
+ tomk = rambits*16*1024 - 32768;
/* Compute the top of Low memory */
tolmk = pci_tolm >> 10;
if (tolmk >= tomk) {
@@ -232,6 +239,8 @@
static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
{
+ printk_spew("Entering vt8623 pci_domain_scan_bus.\n");
+
max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
return max;
}
@@ -263,7 +272,7 @@
static void enable_dev(struct device *dev)
{
- struct device_path path;
+ printk_spew("In vt8623 enable_dev for device %s.\n", dev_path(dev));
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
@@ -275,7 +284,7 @@
}
}
-struct chip_operations northbridge_via_vt8623_control = {
+struct chip_operations northbridge_via_vt8623_ops = {
CHIP_NAME("VIA vt8623 Northbridge")
.enable_dev = enable_dev,
};
diff -ruN LinuxBIOSv2.04/src/northbridge/via/vt8623/raminit.c LinuxBIOSv2.05/src/northbridge/via/vt8623/raminit.c
--- LinuxBIOSv2.04/src/northbridge/via/vt8623/raminit.c 2005-08-03 15:13:16.862358000 +0100
+++ LinuxBIOSv2.05/src/northbridge/via/vt8623/raminit.c 2005-08-03 18:01:40.397790250 +0100
@@ -110,7 +110,7 @@
north = pci_locate_device(PCI_ID(0x1106, 0x3123), 0);
north = 0;
print_debug_hex32(north);
- print_debug(" is the north\n");
+ print_debug(" is the north\r\n");
print_debug_hex16(pci_read_config16(north, 0));
print_debug(" ");
print_debug_hex16(pci_read_config16(north, 2));
@@ -250,7 +250,7 @@
val = (Trp << 7) | (Tras << 6) | (casl << 4) | 4;
- print_debug_hex8(val); print_debug(" is the computed timing\n");
+ print_debug_hex8(val); print_debug(" is the computed timing\r\n");
/* don't set it. Experience shows that this screwy chipset should just
* be run with the most conservative timing.
* pci_write_config8(0, 0x64, val);
-------------- next part --------------
diff -ruN LinuxBIOSv2.05/src/mainboard/via/epia-m/Config.lb LinuxBIOSv2.06/src/mainboard/via/epia-m/Config.lb
--- LinuxBIOSv2.05/src/mainboard/via/epia-m/Config.lb 2005-08-03 16:35:39.375246000 +0100
+++ LinuxBIOSv2.06/src/mainboard/via/epia-m/Config.lb 2005-08-03 18:15:51.238964500 +0100
@@ -145,6 +145,30 @@
device pci 10.3 on end # USB 2
device pci 11.0 on # Southbridge
+ chip superio/via/vt1211
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ drq 0x74 = 3
+ end
+ device pnp 2e.2 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 on # COM2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.b on # HWM
+ io 0x60 = 0xec00
+ end
+
+ end
end
device pci 11.1 on end # IDE
@@ -153,12 +177,6 @@
device pci 11.6 off end # AC97 Modem
device pci 12.0 on end # Ethernet
end
- chip superio/via/vt1211
- register "enable_com_ports" = "1"
- register "enable_hwmon" = "1"
- register "enable_lpt" = "1"
- register "enable_fdc" = "1"
- end
# This is on the EPIA MII, not the M.
# chip southbridge/ricoh/rl5c476
# end
diff -ruN LinuxBIOSv2.05/src/superio/via/vt1211/chip.h LinuxBIOSv2.06/src/superio/via/vt1211/chip.h
--- LinuxBIOSv2.05/src/superio/via/vt1211/chip.h 2005-08-03 15:12:49.108624000 +0100
+++ LinuxBIOSv2.06/src/superio/via/vt1211/chip.h 2005-08-03 18:16:33.913631500 +0100
@@ -1,19 +1,12 @@
#ifndef _SUPERIO_VIA_VT1211
#define _SUPERIO_VIA_VT1211
-extern struct chip_operations superio_via_vt1211_control;
+#include <uart8250.h>
+
+extern struct chip_operations superio_via_vt1211_ops;
struct superio_via_vt1211_config {
- /* PCI function enables */
- /* i.e. so that pci scan bus will find them. */
- /* I am putting in IDE as an example but obviously this needs
- * to be more complete!
- */
- /* enables of functions of devices */
- int enable_com_ports;
- int enable_fdc;
- int enable_lpt;
- int enable_hwmon;
+ struct uart8250 com1, com2;
};
#endif /* _SUPERIO_VIA_VT1211 */
diff -ruN LinuxBIOSv2.05/src/superio/via/vt1211/vt1211.c LinuxBIOSv2.06/src/superio/via/vt1211/vt1211.c
--- LinuxBIOSv2.05/src/superio/via/vt1211/vt1211.c 2005-08-03 15:12:49.108624000 +0100
+++ LinuxBIOSv2.06/src/superio/via/vt1211/vt1211.c 2005-08-03 18:16:43.054202750 +0100
@@ -22,11 +22,11 @@
#include <arch/io.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ops.h>
-#include <device/pci_ids.h>
#include <console/console.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <uart8250.h>
+
#include "vt1211.h"
#include "chip.h"
@@ -47,102 +47,120 @@
0x4c,0x0, 0x4d,0x0, 0x4e,0xf, 0x5d,0x77,
0x5c,0x0, 0x5f,0x33, 0x40,0x1};
-static void start_conf_pnp(int dev)
-{
- outb(0x87,0x2e);
- outb(0x87,0x2e);
- outb(7,0x2e);
- outb(dev,0x2f);
-}
-static void write_pnp(int reg, int val)
+static void pnp_enter_ext_func_mode(device_t dev)
{
- outb(reg,0x2e);
- outb(val,0x2f);
+ outb(0x87, dev->path.u.pnp.port);
+ outb(0x87, dev->path.u.pnp.port);
}
-static void end_conf_pnp()
+
+static void pnp_exit_ext_func_mode(device_t dev)
{
- outb(0xaa,0x2e);
+ outb(0xaa, dev->path.u.pnp.port);
}
-static void vt1211_init(struct superio_via_vt1211_config *conf)
+static void init_hwm(unsigned long base)
{
-
int i;
- // Activate the vt1211 hardware monitor
- if(conf->enable_hwmon){
- start_conf_pnp(0x0b);
- write_pnp(0x60,0xec);
- write_pnp(0x30,1);
- end_conf_pnp();
-
- // initialize vt1211 hardware monitor registers, which are at 0xECXX
- for(i=0;i<sizeof(vt1211hwmonitorinits);i+=2)
- outb(vt1211hwmonitorinits[i+1],0xec00+vt1211hwmonitorinits[i]);
- }
- if( conf->enable_fdc){
- // activate FDC
- start_conf_pnp(0); // fdc is device 0
- write_pnp(0x60,0xfc); // io address
- write_pnp(0x70,0x06); // interupt
- write_pnp(0x74,0x02); // dma
- write_pnp(0x30,0x01); // activate it
- end_conf_pnp();
- }
-
- if( conf->enable_com_ports ){
- // activate com2
- start_conf_pnp(3);
- write_pnp(0x60,0xbe);
- write_pnp(0x70,0x3);
- write_pnp(0xf0,0x02);
- write_pnp(0x30,0x01);
- end_conf_pnp();
- }
- if( conf->enable_lpt ){
- // activate lpt
- start_conf_pnp(1);
- write_pnp(0x60,0xde);
- write_pnp(0x70,0x07);
- write_pnp(0x74,0x3);
- write_pnp(0x30,0x01);
- end_conf_pnp();
+ // initialize vt1211 hardware monitor registers, which are at 0xECXX
+ for(i = 0; i < sizeof(vt1211hwmonitorinits); i += 2) {
+ outb(vt1211hwmonitorinits[i + 1],
+ base + vt1211hwmonitorinits[i]);
}
-
}
-static void superio_init(struct chip *chip, enum chip_pass pass)
+static void vt1211_init(struct device *dev)
{
+ struct superio_via_vt1211_config *conf = dev->chip_info;
+ struct resource *res0;
- struct superio_via_vt1211_config *conf =
- (struct superio_via_vt1211_config *)chip->chip_info;
+ if (!dev->enabled) {
+ return;
+ }
- switch (pass) {
- case CONF_PASS_PRE_PCI:
+ switch (dev->path.u.pnp.device) {
+ case VT1211_SP1:
+ res0 = find_resource(dev, PNP_IDX_IO0);
+ init_uart8250(res0->base, &conf->com1);
break;
-
- case CONF_PASS_POST_PCI:
- vt1211_init(conf);
+ case VT1211_SP2:
+ res0 = find_resource(dev, PNP_IDX_IO0);
+ init_uart8250(res0->base, &conf->com2);
break;
-
- case CONF_PASS_PRE_BOOT:
+ case VT1211_HWM:
+ res0 = find_resource(dev, PNP_IDX_IO0);
+ init_hwm(res0->base);
break;
-
default:
- /* nothing yet */
- break;
+ printk_info("vt1211 asked to initialise unknown device!\n");
}
+
+ /* activate com2
+ start_conf_pnp(3);
+ write_pnp(0x60,0xbe);
+ write_pnp(0x70,0x3);
+ write_pnp(0xf0,0x02);
+ write_pnp(0x30,0x01);
+ end_conf_pnp();
+
+ // Activate the vt1211 hardware monitor
+ start_conf_pnp(0x0b);
+ write_pnp(0x60,0xec);
+ write_pnp(0x30,1);
+ end_conf_pnp(); */
+
+}
+
+void vt1211_pnp_enable_resources(device_t dev)
+{
+ pnp_enter_ext_func_mode(dev);
+ pnp_enable_resources(dev);
+ pnp_exit_ext_func_mode(dev);
}
-static void enumerate(struct chip *chip)
+void vt1211_pnp_set_resources(struct device *dev)
+{
+ pnp_enter_ext_func_mode(dev);
+ pnp_set_resources(dev);
+ pnp_exit_ext_func_mode(dev);
+}
+
+void vt1211_pnp_enable(device_t dev)
+{
+ if (!dev->enabled) {
+ pnp_enter_ext_func_mode(dev);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_exit_ext_func_mode(dev);
+ }
+}
+
+struct device_operations ops = {
+ .read_resources = pnp_read_resources,
+ .set_resources = vt1211_pnp_set_resources,
+ .enable_resources = vt1211_pnp_enable_resources,
+ .enable = vt1211_pnp_enable,
+ .init = vt1211_init,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+ { &ops, VT1211_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
+ { &ops, VT1211_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
+ { &ops, VT1211_SP1, PNP_IO0 | PNP_IRQ0, { 0x07f8, 0}, },
+ { &ops, VT1211_SP2, PNP_IO0 | PNP_IRQ0, { 0x07f8, 0}, },
+ { &ops, VT1211_HWM, PNP_IO0 , { 0xfff8, 0 }, },
+};
+
+static void enable_dev(struct device *dev)
{
- extern struct device_operations default_pci_ops_bus;
- chip_enumerate(chip);
- chip->dev->ops = &default_pci_ops_bus;
+ printk_debug("vt1211 enabling PNP devices.\n");
+ pnp_enable_devices(dev,
+ &ops,
+ sizeof(pnp_dev_info) / sizeof(pnp_dev_info[0]),
+ pnp_dev_info);
}
-struct chip_operations superio_via_vt1211_control = {
+struct chip_operations superio_via_vt1211_ops = {
CHIP_NAME("VIA vt1211")
- .enumerate = enumerate,
- .enable = superio_init,
+ .enable_dev = enable_dev,
};
diff -ruN LinuxBIOSv2.05/src/superio/via/vt1211/vt1211.h LinuxBIOSv2.06/src/superio/via/vt1211/vt1211.h
--- LinuxBIOSv2.05/src/superio/via/vt1211/vt1211.h 2005-08-03 15:12:49.108624000 +0100
+++ LinuxBIOSv2.06/src/superio/via/vt1211/vt1211.h 2005-08-03 18:16:50.502668250 +0100
@@ -18,5 +18,17 @@
* MA 02111-1307 USA
*/
- /* vt1211 routines and defines*/
+/* vt1211 PNP devices */
+#define VT1211_FDC 0 /* Floppy */
+#define VT1211_PP 1 /* Parallel Port */
+#define VT1211_SP1 2 /* COM1 */
+#define VT1211_SP2 3 /* COM2 */
+#define VT1211_MIDI 6 /* MIDI */
+#define VT1211_GAME 7 /* Game port */
+#define VT1211_GPIO 8 /* GPIO pins */
+#define VT1211_WATCHDOG 9 /* Watchdog timer */
+#define VT1211_WAKEUP 10 /* Wakeup control */
+#define VT1211_HWM 11 /* Hardware monitor */
+#define VT1211_FIR 12 /* Irda */
+#define VT1211_ROM 13 /* ROM control */
-------------- next part --------------
diff -ruN LinuxBIOSv2.orig/src/mainboard/via/epia-m/Options.lb LinuxBIOSv2.01/src/mainboard/via/epia-m/Options.lb
--- LinuxBIOSv2.orig/src/mainboard/via/epia-m/Options.lb 2005-08-03 15:12:56.161065000 +0100
+++ LinuxBIOSv2.01/src/mainboard/via/epia-m/Options.lb 2005-08-03 15:43:21.287128250 +0100
@@ -32,6 +32,9 @@
uses CC
uses HOSTCC
uses OBJCOPY
+uses DEFAULT_CONSOLE_LOGLEVEL
+uses MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_CONSOLE_SERIAL8250
## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE = 256*1024
diff -ruN LinuxBIOSv2.orig/targets/via/epia-m/Config.512kflash.lb LinuxBIOSv2.01/targets/via/epia-m/Config.512kflash.lb
--- LinuxBIOSv2.orig/targets/via/epia-m/Config.512kflash.lb 2005-08-03 15:13:31.827294000 +0100
+++ LinuxBIOSv2.01/targets/via/epia-m/Config.512kflash.lb 2005-08-03 15:42:26.515705250 +0100
@@ -1,64 +1,14 @@
# Sample config file for EPIA-M
# This will make a target directory of ./epia-m.512kflash
-loadoptions
-
target epia-m.512kflash
-uses ARCH
-uses CONFIG_COMPRESS
-uses CONFIG_IOAPIC
-uses CONFIG_ROM_STREAM
-uses CONFIG_ROM_STREAM_START
-uses CONFIG_UDELAY_TSC
-uses CPU_FIXUP
-uses FALLBACK_SIZE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_MP_TABLE
-uses HAVE_PIRQ_TABLE
-uses HAVE_HARD_RESET
-uses i586
-uses i686
-uses INTEL_PPRO_MTRR
-uses HEAP_SIZE
-uses IRQ_SLOT_COUNT
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-uses CONFIG_SMP
-uses CONFIG_MAX_CPUS
-uses MEMORY_HOLE
-uses PAYLOAD_SIZE
-uses _RAMBASE
-uses _ROMBASE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_OFFSET
-uses ROM_SECTION_SIZE
-uses ROM_SIZE
-uses STACK_SIZE
-uses USE_FALLBACK_IMAGE
-uses USE_OPTION_TABLE
-uses HAVE_OPTION_TABLE
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses MAINBOARD
-uses CONFIG_CHIP_CONFIGURE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses LINUXBIOS_EXTRA_VERSION
-
-option CONFIG_CHIP_CONFIGURE=1
+mainboard via/epia-m
option MAXIMUM_CONSOLE_LOGLEVEL=8
option DEFAULT_CONSOLE_LOGLEVEL=8
option CONFIG_CONSOLE_SERIAL8250=1
-option CPU_FIXUP=1
-option CONFIG_UDELAY_TSC=0
-option i686=1
-option i586=1
-option INTEL_PPRO_MTRR=1
-
option ROM_SIZE=524288
@@ -82,12 +32,12 @@
###
#
-# Arima hdama
+# Via EPIA M
+#
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x10000
option LINUXBIOS_EXTRA_VERSION=".0Normal"
- mainboard via/epia-m
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# payload ../../../../tg3--ide_disk.zelf
payload ../../../../../lnxieepro100.ebi
@@ -97,7 +47,6 @@
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x10000
option LINUXBIOS_EXTRA_VERSION=".0Fallback"
- mainboard via/epia-m
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# payload ../../../../tg3--ide_disk.zelf
payload ../../../../../lnxieepro100.ebi
diff -ruN LinuxBIOSv2.orig/targets/via/epia-m/Config.etherboot.lb LinuxBIOSv2.01/targets/via/epia-m/Config.etherboot.lb
--- LinuxBIOSv2.orig/targets/via/epia-m/Config.etherboot.lb 2005-08-03 15:13:31.831294000 +0100
+++ LinuxBIOSv2.01/targets/via/epia-m/Config.etherboot.lb 2005-08-03 15:42:14.638963000 +0100
@@ -1,66 +1,14 @@
# Sample config file for EPIA-M
# This will make a target directory of ./epia-m
-loadoptions
-
target epia-m
-uses ARCH
-uses CONFIG_COMPRESS
-uses CONFIG_IOAPIC
-uses CONFIG_ROM_STREAM
-uses CONFIG_ROM_STREAM_START
-uses CONFIG_UDELAY_TSC
-uses CPU_FIXUP
-uses FALLBACK_SIZE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_MP_TABLE
-uses HAVE_PIRQ_TABLE
-uses HAVE_HARD_RESET
-uses i586
-uses i686
-uses INTEL_PPRO_MTRR
-uses HEAP_SIZE
-uses IRQ_SLOT_COUNT
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-uses CONFIG_SMP
-uses CONFIG_MAX_CPUS
-uses MEMORY_HOLE
-uses PAYLOAD_SIZE
-uses _RAMBASE
-uses _ROMBASE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_OFFSET
-uses ROM_SECTION_SIZE
-uses ROM_SIZE
-uses STACK_SIZE
-uses USE_FALLBACK_IMAGE
-uses USE_OPTION_TABLE
-uses HAVE_OPTION_TABLE
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses MAINBOARD
-uses CONFIG_CHIP_CONFIGURE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses LINUXBIOS_EXTRA_VERSION
-uses TTYS0_BAUD
-
-option TTYS0_BAUD=19200
+mainboard via/epia-m
-option CONFIG_CHIP_CONFIGURE=1
-
-option MAXIMUM_CONSOLE_LOGLEVEL=7
-option DEFAULT_CONSOLE_LOGLEVEL=7
+option MAXIMUM_CONSOLE_LOGLEVEL=8
+option DEFAULT_CONSOLE_LOGLEVEL=8
option CONFIG_CONSOLE_SERIAL8250=1
-option CPU_FIXUP=1
-option CONFIG_UDELAY_TSC=0
-option i686=1
-option i586=1
-option INTEL_PPRO_MTRR=1
option ROM_SIZE=256*1024
option HAVE_OPTION_TABLE=1
@@ -83,12 +31,12 @@
###
#
-# Arima hdama
+# Via EPIA-M
+#
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x10000
option LINUXBIOS_EXTRA_VERSION=".0Normal"
- mainboard via/epia-m
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# payload ../../../../tg3--ide_disk.zelf
payload ../../../../../lnxieepro100.ebi
@@ -98,7 +46,6 @@
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x10000
option LINUXBIOS_EXTRA_VERSION=".0Fallback"
- mainboard via/epia-m
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# payload ../../../../tg3--ide_disk.zelf
payload ../../../../../lnxieepro100.ebi
diff -ruN LinuxBIOSv2.orig/targets/via/epia-m/Config.filo.lb LinuxBIOSv2.01/targets/via/epia-m/Config.filo.lb
--- LinuxBIOSv2.orig/targets/via/epia-m/Config.filo.lb 2005-08-03 15:13:31.827294000 +0100
+++ LinuxBIOSv2.01/targets/via/epia-m/Config.filo.lb 2005-08-03 15:41:56.421824500 +0100
@@ -1,63 +1,14 @@
# Sample config file for EPIA-M
# This will make a target directory of ./epia-m
-loadoptions
-
target epia-m
-uses ARCH
-uses CONFIG_COMPRESS
-uses CONFIG_IOAPIC
-uses CONFIG_ROM_STREAM
-uses CONFIG_ROM_STREAM_START
-uses CONFIG_UDELAY_TSC
-uses CPU_FIXUP
-uses FALLBACK_SIZE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_MP_TABLE
-uses HAVE_PIRQ_TABLE
-uses HAVE_HARD_RESET
-uses i586
-uses i686
-uses INTEL_PPRO_MTRR
-uses HEAP_SIZE
-uses IRQ_SLOT_COUNT
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-uses CONFIG_SMP
-uses CONFIG_MAX_CPUS
-uses MEMORY_HOLE
-uses PAYLOAD_SIZE
-uses _RAMBASE
-uses _ROMBASE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_OFFSET
-uses ROM_SECTION_SIZE
-uses ROM_SIZE
-uses STACK_SIZE
-uses USE_FALLBACK_IMAGE
-uses USE_OPTION_TABLE
-uses HAVE_OPTION_TABLE
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses MAINBOARD
-uses CONFIG_CHIP_CONFIGURE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses LINUXBIOS_EXTRA_VERSION
-
-option CONFIG_CHIP_CONFIGURE=1
+mainboard via/epia-m
option MAXIMUM_CONSOLE_LOGLEVEL=8
option DEFAULT_CONSOLE_LOGLEVEL=8
option CONFIG_CONSOLE_SERIAL8250=1
-option CPU_FIXUP=1
-option CONFIG_UDELAY_TSC=0
-option i686=1
-option i586=1
-option INTEL_PPRO_MTRR=1
option ROM_SIZE=256*1024
option HAVE_OPTION_TABLE=1
@@ -80,12 +31,12 @@
###
#
-# Arima hdama
+# EPIA-M
+#
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x10000
option LINUXBIOS_EXTRA_VERSION=".0Normal"
- mainboard via/epia-m
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# payload ../../../../tg3--ide_disk.zelf
# payload ../../../../../lnxieepro100.ebi
@@ -96,7 +47,6 @@
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x10000
option LINUXBIOS_EXTRA_VERSION=".0Fallback"
- mainboard via/epia-m
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# payload ../../../../tg3--ide_disk.zelf
# payload ../../../../../lnxieepro100.ebi
diff -ruN LinuxBIOSv2.orig/targets/via/epia-m/Config.lb LinuxBIOSv2.01/targets/via/epia-m/Config.lb
--- LinuxBIOSv2.orig/targets/via/epia-m/Config.lb 2005-08-03 15:13:31.827294000 +0100
+++ LinuxBIOSv2.01/targets/via/epia-m/Config.lb 2005-08-04 18:37:09.614520500 +0100
@@ -1,78 +1,24 @@
# Sample config file for EPIA-M
# This will make a target directory of ./epia-m
-loadoptions
-
target epia-m
-uses ARCH
-uses CONFIG_COMPRESS
-uses CONFIG_IOAPIC
-uses CONFIG_ROM_STREAM
-uses CONFIG_ROM_STREAM_START
-uses CONFIG_UDELAY_TSC
-uses CPU_FIXUP
-uses FALLBACK_SIZE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_MP_TABLE
-uses HAVE_PIRQ_TABLE
-uses HAVE_HARD_RESET
-uses i586
-uses i686
-uses INTEL_PPRO_MTRR
-uses HEAP_SIZE
-uses IRQ_SLOT_COUNT
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-uses CONFIG_SMP
-uses CONFIG_MAX_CPUS
-uses MEMORY_HOLE
-uses PAYLOAD_SIZE
-uses _RAMBASE
-uses _ROMBASE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_OFFSET
-uses ROM_SECTION_SIZE
-uses ROM_SIZE
-uses STACK_SIZE
-uses USE_FALLBACK_IMAGE
-uses USE_OPTION_TABLE
-uses HAVE_OPTION_TABLE
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses MAINBOARD
-uses CONFIG_CHIP_CONFIGURE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses LINUXBIOS_EXTRA_VERSION
-uses HAVE_ACPI_TABLES
-uses CONFIG_LEGACY_VGABIOS
-uses VGABIOS_START
-uses VGABIOS_START
-option CONFIG_CHIP_CONFIGURE=1
+mainboard via/epia-m
option MAXIMUM_CONSOLE_LOGLEVEL=8
option DEFAULT_CONSOLE_LOGLEVEL=8
option CONFIG_CONSOLE_SERIAL8250=1
-option HAVE_ACPI_TABLES=1
-option CPU_FIXUP=1
-option CONFIG_UDELAY_TSC=0
-option i686=1
-option i586=1
-option INTEL_PPRO_MTRR=1
+
option ROM_SIZE=256*1024
-option CONFIG_LEGACY_VGABIOS=1
option HAVE_OPTION_TABLE=1
option CONFIG_ROM_STREAM=1
option HAVE_FALLBACK_BOOT=1
-option VGABIOS_START=0xfffc0000
###
### Compute the location and size of where this firmware image
### (linuxBIOS plus bootloader) will live in the boot rom chip.
###
-option FALLBACK_SIZE=0x18000
+option FALLBACK_SIZE=131072
## LinuxBIOS C code runs at this location in RAM
option _RAMBASE=0x00004000
@@ -84,29 +30,26 @@
###
#
-# Arima hdama
+# Via EPIA-M
+#
romimage "normal"
option USE_FALLBACK_IMAGE=0
- option ROM_IMAGE_SIZE=0xc000
- option ROM_SECTION_OFFSET=0x10000
- option ROM_SECTION_SIZE=0x18000
+ option ROM_IMAGE_SIZE=0x10000
option LINUXBIOS_EXTRA_VERSION=".0Normal"
- mainboard via/epia-m
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# payload ../../../../tg3--ide_disk.zelf
# payload ../../../../../lnxieepro100.ebi
- payload /filo.elf
+ payload ../../../payloads/filo.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
- option ROM_IMAGE_SIZE=0xc000
+ option ROM_IMAGE_SIZE=0x10000
option LINUXBIOS_EXTRA_VERSION=".0Fallback"
- mainboard via/epia-m
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# payload ../../../../tg3--ide_disk.zelf
# payload ../../../../../lnxieepro100.ebi
- payload /filo.elf
+ payload ../../../payloads/filo.elf
end
buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
diff -ruN LinuxBIOSv2.orig/targets/via/epia-m/Config.vga.filo LinuxBIOSv2.01/targets/via/epia-m/Config.vga.filo
--- LinuxBIOSv2.orig/targets/via/epia-m/Config.vga.filo 2005-08-03 15:13:31.831294000 +0100
+++ LinuxBIOSv2.01/targets/via/epia-m/Config.vga.filo 2005-08-03 15:40:43.593273000 +0100
@@ -1,66 +1,14 @@
# Sample config file for EPIA-M
# This will make a target directory of ./epia-m
-loadoptions
-
target epia-m
-uses ARCH
-uses CONFIG_COMPRESS
-uses CONFIG_IOAPIC
-uses CONFIG_ROM_STREAM
-uses CONFIG_ROM_STREAM_START
-uses CONFIG_UDELAY_TSC
-uses CPU_FIXUP
-uses FALLBACK_SIZE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_MP_TABLE
-uses HAVE_PIRQ_TABLE
-uses HAVE_HARD_RESET
-uses i586
-uses i686
-uses INTEL_PPRO_MTRR
-uses HEAP_SIZE
-uses IRQ_SLOT_COUNT
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-uses CONFIG_SMP
-uses CONFIG_MAX_CPUS
-uses MEMORY_HOLE
-uses PAYLOAD_SIZE
-uses _RAMBASE
-uses _ROMBASE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_OFFSET
-uses ROM_SECTION_SIZE
-uses ROM_SIZE
-uses STACK_SIZE
-uses USE_FALLBACK_IMAGE
-uses USE_OPTION_TABLE
-uses HAVE_OPTION_TABLE
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses MAINBOARD
-uses CONFIG_CHIP_CONFIGURE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses LINUXBIOS_EXTRA_VERSION
-uses HAVE_ACPI_TABLES
-uses CONFIG_LEGACY_VGABIOS
-uses VGABIOS_START
-uses VGABIOS_START
-option CONFIG_CHIP_CONFIGURE=1
+mainboard via/epia-m
option MAXIMUM_CONSOLE_LOGLEVEL=8
option DEFAULT_CONSOLE_LOGLEVEL=8
option CONFIG_CONSOLE_SERIAL8250=1
-option HAVE_ACPI_TABLES=1
-option CPU_FIXUP=1
-option CONFIG_UDELAY_TSC=0
-option i686=1
-option i586=1
-option INTEL_PPRO_MTRR=1
+
option ROM_SIZE=256*1024
option CONFIG_LEGACY_VGABIOS=1
option HAVE_OPTION_TABLE=1
@@ -84,14 +32,14 @@
###
#
-# Arima hdama
+# EPIA-M
+#
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0xc000
option ROM_SECTION_OFFSET=0x10000
option ROM_SECTION_SIZE=0x18000
option LINUXBIOS_EXTRA_VERSION=".0Normal"
- mainboard via/epia-m
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# payload ../../../../tg3--ide_disk.zelf
# payload ../../../../../lnxieepro100.ebi
@@ -102,7 +50,6 @@
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0xc000
option LINUXBIOS_EXTRA_VERSION=".0Fallback"
- mainboard via/epia-m
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# payload ../../../../tg3--ide_disk.zelf
# payload ../../../../../lnxieepro100.ebi
Binary files LinuxBIOSv2.orig/util/newconfig/yappsrt.pyc and LinuxBIOSv2.01/util/newconfig/yappsrt.pyc differ
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