PCI configuration question

[Li-Ta Lo]

On Wed, 2004-09-15 at 04:00, Eric W. Biederman wrote:
> Liu Tao <liutao at safe-mail.net> writes:
> 
> > Hello all,
> > 
> > In the LinuxBIOS-AMD64 document the author explains the "pci" keyword
> >  >  The first occurrence of the pci keyword tells LinuxBIOS where the bridge
> > device start,
> >  >  relative to PCI configuration space used by the bridge. The following
> > occurences of
> >  >  the pci keyword describe the provided devices.
> > 
> > then gives an example
> >  >  northbridge amd/amdk8 "mc1"
> >  >          pci 0:19.0
> >  >          pci 0:19.0
> >  >          pci 0:19.0
> >  >          pci 0:19.1
> >  >          pci 0:19.2
> >  >          pci 0:19.3
> >  >  end
> > 
> > I'm not clear why the example repeate "pci 0:19.0" three times?
> > I noticed in chip.c the chip_enumerate() function checks the same path
> >  >        identical_paths = (i > 0) && (path_eq(&chip->path[i - 1].path,
> > &chip->path[i].path));
> > but I can't find out the real intent.
> 
> Because I need some way of showing there are 3 hypertransport links.
> With just one I don't have enough places to hang the devices off of.

That is why I said that the word link is heavily overloaded and 
confusing. Sometimes it means Hypertransport links and sometimes
it means PCI bus. And I am pretty sure HT links != PCI bus.

>  
> > Another question maybe related to the former one is, in "device" structure
> > what does the "link[MAX_LINKS]" and "links" member describe?
> > Does "link[MAX_LINKS]" describes the secondary or subordinate bus of a bridge
> > device?
> > Why MAX_LINKS is defined to 3?
> 
> Because that is the largest number of links I have ever had hanging off of
> one device.
> 

With AMD proposing dual core and HT hypercube is it going to be true 
in the near future ?

Ollie