FYI: Merge in progress...

[YhLu]

Amd_early_mtrr.c

#ifndef AMD_EARLYMTRR_C
#define AMD_EARLYMTRR_C
#include <cpu/x86/mtrr.h>
#include <cpu/amd/mtrr.h>
#include "cpu/x86/mtrr/earlymtrr.c"

static void amd_early_mtrr_init(void)
{
        static const unsigned long mtrr_msrs[] = {
                /* fixed mtrr */
                0x250, 0x258, 0x259,
                0x268, 0x269, 0x26A,
                0x26B, 0x26C, 0x26D,
                0x26E, 0x26F,
                /* var mtrr */
                0x200, 0x201, 0x202, 0x203,
                0x204, 0x205, 0x206, 0x207,
                0x208, 0x209, 0x20A, 0x20B,
                0x20C, 0x20D, 0x20E, 0x20F,
                /* var iorr msr */
                0xC0010016, 0xC0010017, 0xC0010018, 0xC0010019,
                /* mem top */
                0xC001001A, 0xC001001D,
                /* NULL end of table */
                0
        };
        msr_t msr;
        const unsigned long *msr_addr;

        /* Enable the access to AMD RdDram and WrDram extension bits */
        msr = rdmsr(SYSCFG_MSR);
        msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
        wrmsr(SYSCFG_MSR, msr);

        /* Inialize all of the relevant msrs to 0 */
        msr.lo = 0;
        msr.hi = 0;

        for (msr_addr = mtrr_msrs; *msr_addr; msr_addr++) {
                wrmsr(*msr_addr, msr);
        }

        /* Disable the access to AMD RdDram and WrDram extension bits */
        msr = rdmsr(SYSCFG_MSR);
        msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
        wrmsr(SYSCFG_MSR, msr);

        /* Enable memory access for 0 - 1MB using top_mem */
        msr.hi = 0;
        msr.lo = ((CONFIG_LB_MEM_TOPK << 10) + TOP_MEM_MASK) &
~TOP_MEM_MASK;
        wrmsr(TOP_MEM, msr);

        /* Enable caching for 0 - 1MB using variable mtrr */
        set_var_mtrr(0, 0, (CONFIG_LB_MEM_TOPK << 10), MTRR_TYPE_WRBACK);

#if defined(XIP_ROM_SIZE)
        /* enable write through caching so we can do execute in place
         * on the flash rom.
         */
        set_var_mtrr(1, XIP_ROM_BASE, XIP_ROM_SIZE, MTRR_TYPE_WRBACK);
#endif

        /* Set the default memory type and enable fixed and variable MTRRs 
         */
        /* Enable Variable MTRRs */
        msr.hi = 0x00000000;
        msr.lo = 0x00000800;
        wrmsr(MTRRdefType_MSR, msr);

        /* Enale the MTRRs in SYSCFG */
        msr = rdmsr(SYSCFG_MSR);
        msr.lo |= SYSCFG_MSR_MtrrVarDramEn;
        wrmsr(SYSCFG_MSR, msr);

        /* Enable the cache */
        enable_cache();
}

#endif /* AMD_EARLYMTRR_C */