[BULK] Re: changes today.

[YhLu]

> 4. better ht_setup_chainx() in incoherent_ht.c ---> change share bus 0 to
 different bus for different incoherent HT link.
For s2885 there are two incoherent links in CPU0, one for 8151 and one for
8131/8111.
For AMD/quartet are incoherent link in CPU0, and another link in CPU1
For S2895 there are two incoherent links in CPU0 and another link in CPU1.
 
For S2885, in old ht_setup_chains, I let the two links share bus 0, 
So 
         PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x06010207,
         PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000007,
But if there is too much link, will used the device num.
 
So update the ht_setup_chains
 
 
static int ht_setup_chains(const struct ht_chain *ht_c, int ht_c_num)
{
        /* Assumption the HT chain that is bus 0 has the HT I/O Hub on it. 
         * On most boards this just happens.  If a cpu has multiple
         * non Coherent links the appropriate bus registers for the
         * links needs to be programed to point at bus 0.
         */
        int reset_needed;
        unsigned upos;
        device_t udev;
        int i;
 
        reset_needed = 0;
 
        for (i = 0; i < ht_c_num; i++) {
                uint32_t reg;
                unsigned devpos;
                unsigned regpos;
                uint32_t dword;
                unsigned busn;
 
                reg = pci_read_config32(PCI_DEV(0,0x18,1), ht_c[i].devreg);
 
                //We need setup 0x94, 0xb4, and 0xd4 according to the reg
                devpos = ((reg & 0xf0)>>4)+0x18; // nodeid; it will decide
0x18 or 0x19
                regpos = ((reg & 0xf00)>>8) * 0x20 + 0x94; // link n; it
will decide 0x94 or 0xb4, 0x0xd4;
                busn = (reg & 0xff0000)>>16;
 
                dword = pci_read_config32( PCI_DEV(0, devpos, 0), regpos) ;
                dword &= ~(0xffff<<8);
                dword |= (reg & 0xffff0000)>>8;
                pci_write_config32( PCI_DEV(0, devpos,0), regpos , dword);
 
                /* Make certain the HT bus is not enumerated */
                ht_collapse_previous_enumeration(busn);
 
                upos = ht_c[i].upos;
                udev = ht_c[i].udev;
               reset_needed |= ht_setup_chainx(udev,upos,busn );
 
        }
 
        return reset_needed;
}
 
 
> 5. fix one bug about io and mem allocation for multi ht links. --- in
> northbridge.c
Should mark some reg to prevent the overlap.
Because amdk8_find_mempair and amdk8_find_iopair are called several times
(for the incoherent links), before the registers are set.
So same reg will be assigned to different link. That is bug, So add some
thing in the PCI reg.
 
        /* Mark reg has been used now */
        base = f1_read_config32(reg);
        if( (base & 3) != 3 ) {
                base |= 0x01fff000;
                f1_write_config32(reg, base);
        }
 
        /* Mark reg has been used now */
        base = f1_read_config32(reg);
        if( (base & 3) != 3 ) {
                base |= 0xffffff00;
                f1_write_config32(reg, base);
        }
 
Regards
 
YH
 
 
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