What's next?

Stefan Reinauer stepan at openbios.org
Tue Nov 30 12:04:00 CET 2004


* Yinghai Lu <yhlu at tyan.com> [041126 06:13]:
> What is your HT topology?
> 
> Is there any cross link between (CPU0 and CPU2) or (CPU1 and CPU2)....

0-2 is there, did you mean 0-3/1-2?

Actually the specs I got had a different CPU numbering, but the existing
non-linux bios works with below topology...

static const unsigned int rows_4p[4][4] = {
    { 0x000b0101, 0x00010202, 0x00030808, 0x00010208 },
    { 0x00010202, 0x00070101, 0x00010204, 0x00030404 },
    { 0x00030404, 0x00010204, 0x00070101, 0x00010202 },
    { 0x00010208, 0x00030808, 0x00010202, 0x000b0101 }
};


NCHT-chain              NCHT-chain
    |                       |
    |                       |
   LDT2                    LDT1
    |                       |
   CPU2 - LDT0 ---- LDT0 - CPU3
    |                       |
   LDT1                    LDT2
    |                       |
    |                       |
    |                       |
   LDT2                    LDT1
    |                       |
   CPU0 - LDT0 ---- LDT0 - CPU1
    |                       |
   LDT1                    LDT2
    |                       |
    |                       |
NCHT-chain              NCHT-chain

> You may try to disable i2c stuff in the amd8111 dir.

Tried this already. Doesn't help. I also tried disabling the link
optimization code, but as one would assume, it does not play in until
softreset, which it never reaches.

> The code works well with S4882 and S4880.

  ... Stefan




More information about the coreboot mailing list