Cache On and ECC clear
rminnich at lanl.gov
Sun Mar 28 23:41:39 CEST 2004
On 28 Mar 2004, Eric W. Biederman wrote:
> But please break it out into it's own separate inline function.
> It has two very strong requirements.
> 1) That we never trigger a hardware read on the addresses were are clearing
> before we have triggered a hardware write. The fact I setup the area
> as uncached but write-combining ensures this.
> 2) That this code runs very fast. It needs to be able to run at 6.4GB/s
> when you have dual channel PC3200 DDR installed. This is one of the
> reasons we run it on a per cpu basis. The loop can only run at 4.0GB/s
> from the other cpu.
ok, if it stays assembly this explanation will be put in with it.
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