Cache On and ECC clear

Eric W. Biederman ebiederman at
Sun Mar 28 17:14:00 CEST 2004

ron minnich <rminnich at> writes:

> On 26 Mar 2004, Eric W. Biederman wrote:
> > 
> > Mostly it was just a copy from the romcc code.  And I have
> > a little distrust of compilers when I want a tight loop.
> for clarity and keep our other 3rd parties happy that's going to become C, 
> hope nobody minds.

Fine, I think.  

But please break it out into it's own separate inline function.

It has two very strong requirements.
1) That we never trigger a hardware read on the addresses were are clearing
   before we have triggered a hardware write.  The fact I setup the area
   as uncached but write-combining ensures this.
2) That this code runs very fast.  It needs to be able to run at 6.4GB/s
   when you have dual channel PC3200 DDR installed.  This is one of the
   reasons we run it on a per cpu basis.  The loop can only run at 4.0GB/s
   from the other cpu.

When we don't need the fine grained control of assembly to meet these
requirements I don't have a problem with writing the code in C.  When
we do need the control we must be able to write it.

In part booting faster boots more correctly because the hardware
transitions from some half setup state to completely setup more


More information about the coreboot mailing list