=?gb2312?b?tPC4tA==?=: Tyan Changes for 1.1.6

Eric W. Biederman ebiederman at lnxi.com
Fri Mar 12 11:55:02 CET 2004

ron minnich <rminnich at lanl.gov> writes:

> On 12 Mar 2004, Eric W. Biederman wrote:
> > Don't enable ECC.
> Or, one thing I'd like to try:
> 	- make sure ECC interrupts are disabled
> 	- enable cache
> 	- clear memory with cache enabled
> 	- cld to make sure it's all flushed
> I am assuming you are writing with cache disabled to avoid ecc errors on 
> loading cache lines. It's a shame we can't do the 'zero-filled cache line' 
> trick that some architectures allow, as you can ZFOD a cache line and 
> blast it out to memory -- or can we do that trick? But I wonder if this 
> other hack would work. Anyone tried it?

I am setting the caching attributes on the memory I am clearing to
Write-Combining in the MTRRs which is better than ZFOD because it
bypasses the cache.  This runs at nearly the theoretical speed of
memory and has done so for years.  This is the way I have always coded
this on x86.  I guess you have not needed to look at that section
of code?

> > I think the Opteron setup now is down to the minimal needed for
> > things to work.  You only observe one reset correct?
> we only see one I think.

The strategy is I setup HT and everything very early with what should
work.  And then in the generic code I come back and redo the
calculations but I don't trigger a reset unless things are incorrect.
So if the early code is complete there should only be a single reset
very early on in the boot process.  If not you will see additional

> > As Ron mentioned later this needs a comment.  In the general case we should
> > not be enabling bus master DMA by default.  I tend to remove bus master
> > enables before remembering any special circumstances of the chip.
> Or dynamically figuring it out would be best. What are the rules here? I 
> have not checked. How would you know to enable this dynamically?

The rules are unless something is a legacy device the device driver
has enough information to enable bus mastering.  Generating interrupts
is part of what bus mastering enables.  The ioapic on the 8131 is
a legacy ISA type device so we need to enable bus mastering in
LinuxBIOS.  The linux kernel does not have enough information to do

> > > 3. Add superio/Winbond/w83627hf.
> > 
> > Thanks that looks correct.  And it was nice to see my changes were
> > that simple to follow.
> Your new pnp stuff looks very well done.

Thanks :)


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