=?gb2312?b?tPC4tA==?=: Tyan Changes for 1.1.6

[ron minnich]

On 12 Mar 2004, Eric W. Biederman wrote:

> Don't enable ECC.

Or, one thing I'd like to try:
	- make sure ECC interrupts are disabled
	- enable cache
	- clear memory with cache enabled
	- cld to make sure it's all flushed

I am assuming you are writing with cache disabled to avoid ecc errors on 
loading cache lines. It's a shame we can't do the 'zero-filled cache line' 
trick that some architectures allow, as you can ZFOD a cache line and 
blast it out to memory -- or can we do that trick? But I wonder if this 
other hack would work. Anyone tried it?

> I think the Opteron setup now is down to the minimal needed for
> things to work.  You only observe one reset correct?

we only see one I think.

> As Ron mentioned later this needs a comment.  In the general case we should
> not be enabling bus master DMA by default.  I tend to remove bus master
> enables before remembering any special circumstances of the chip.

Or dynamically figuring it out would be best. What are the rules here? I 
have not checked. How would you know to enable this dynamically?

> > 3. Add superio/Winbond/w83627hf.
> 
> Thanks that looks correct.  And it was nice to see my changes were
> that simple to follow.

Your new pnp stuff looks very well done.

ron