[Fwd: Re: DiskOnChip Questions]

[Eric W. Biederman]

Michael Robinson <mrobinson at fuzzymuzzle.com> writes:

>  From what I've read on Via's site the EPIAs use a 2/4Mbit ROM, what is the
> limiting factor as to how big the ROM can be?

For an ISA or X-bus part the number of address lines. 
  4Mbit is the limit in a normal 32pin configuration.
For an LPC part the size of the chip you can buy.

AMD and Intel have switched over to using the LPC bus in their
chipsets a year or two ago.  I don't know what VIA has done, but
I expect their are also using the LPC bus by now.

Eric