Using Cache As Ram for K8
Eric W. Biederman
ebiederman at lnxi.com
Fri Jun 25 14:21:01 CEST 2004
Li-Ta Lo <ollie at lanl.gov> writes:
> On Thu, 2004-06-24 at 16:27, Eric W. Biederman wrote:
> > > There are few problems remaining. The first thing is I can only
> > > use 7 cache lines of cache (448 bytes) reliably in the K8. The
> > > access to the 8th cache line is unstable and the access to the
> > > 9th cache line hangs the processor. The other problem is the
> > > optimize_connection() function for multi-processor configuration
> > > runs unstably under CAR. It does not overflow the stack, it's just
> > > plain unstable for some reason. So I can only configure the mainboard
> > > as Uniprocessor.
> > Most likely it is the cross cpu probes, causing cache invalidates.
> > You may be able to ``improperly'' setup caching of memory (no cross
> > cpu probes) while you are initializing the memory controllers.
> That is exactly the point I don't understand. In theory, the AP is
> halted and HT routing disabled on powerup before the first instruction
> is even executed. But to what extend is the processor "halted", does it
> still try to maintain cache coherence ?
Yes. Only the instruction dispatch unit is halted. The other functionality
continues to work. Intel cpus do this to some extent as well. Although
I think a halted processor does is quite.
Look at what disable_probes does in the hypertransport initialization.
Those are the control bits of to see if another cpu is asked about
> And how about the northbridge
> in the processor ? Obviously, the northbridge is in a working state
> when the processor is halted, what is the impact of northbridge on the
> cache of the processor ?
The northbridge should not generate any requests on it's own.
> > On the fun side it would be extremely interesting is if you could get
> > enough memory working to start paging and we could go into 64bit mode :)
> > That is likely tempting fate too much.....
> Why does CAR have anything to do with entering 64bit mode ?
64bit mode can only be entered with paging enabled. With 64K of L1
cache there is enough space to hold the page tables. Roughly
(4K+4K+4K+4K + 4K + 4K) = 24K is needed to map 4G of memory without
using a hack of page table. That is not something we want to use
before some kind of memory is initialized because it would waste rom
space much worse than romcc.
Now that Intel in ``Intel Pentium 4 Processors on 90num Process Specification update''
R28 has let the cat out of the bag I cant vent a little. Intel is formally
supporting cache as ram in their newest cpus, and there have been enough
issues having romcc and not having to worry about them has been a
relief. This may just be a temporary case of teething pains but...
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