Using Cache As Ram for K8

[Li-Ta Lo]

On Thu, 2004-06-24 at 16:27, Eric W. Biederman wrote:
> > There are few problems remaining. The first thing is I can only
> > use 7 cache lines of cache (448 bytes) reliably in the K8. The
> > access to the 8th cache line is unstable and the access to the
> > 9th cache line hangs the processor. The other problem is the
> > optimize_connection() function for multi-processor configuration
> > runs unstably under CAR. It does not overflow the stack, it's just
> > plain unstable for some reason. So I can only configure the mainboard
> > as Uniprocessor.
> 
> Most likely it is the cross cpu probes, causing cache invalidates.
> You may be able to ``improperly'' setup caching of memory (no cross
> cpu probes) while you are initializing the memory controllers.
> 

That is exactly the point I don't understand. In theory, the AP is
halted and HT routing disabled on powerup before the first instruction
is even executed. But to what extend is the processor "halted", does it
still try to maintain cache coherence ? And how about the northbridge
in the processor ? Obviously, the northbridge is in a working state
when the processor is halted, what is the impact of northbridge on the
cache of the processor ?

> On the fun side it would be extremely interesting is if you could get
> enough  memory working to start paging and we could go into 64bit mode :)
> That is likely tempting fate too much.....
> 

Why does CAR have anything to do with entering 64bit mode ?

Ollie