testbios and the system timer

Richard Smith rsmith at bitworks.com
Thu Jun 3 15:10:01 CEST 2004

Peter Stuge wrote:

> On Thu, Jun 03, 2004 at 03:56:29AM -0500, Richard Smith wrote:
>>timer.  In numerious locations my Vbios is writing a 0x00 to IO 0x43 and 
>>then does 2 reads from 0x40.  So its latching the value of counter 0 and 
>>then reading it out.
> Right, it also sets counter mode 0, zero detection interrupt. Are
> there any hints of the code actually using the interrupt anywhere?

Um... I don't know.  What would I look for?  I don't thing so but that 
does explain why linux whines about "too many timer interrutps" occurring.

>>The delay routine is written such that it polls for a rollover to mark 
>>the increment of 838.1 ns.  For this to happen the latch values must be 
>>equal.  In a system where the cpu instructions are running much faster 
>>than one timer clock cycle I guess would not be much of a problem.
> 838.1ns is one tick, not a complete 16-bit rollover, right?

Yeah sorry.  838.1 ns is one tick.  I said rollover which would be 50mS
Re-looking at the delay routine I see I was mistaken as the delay 
routine counts ticks.

Looking at the delay routine is just confusing.  There's a comment that 
says 4 bx counts equals .4290 * 4 or 2uS.  So that tells me the VBios 
thinks the system timer must be running at 2.386 Mhz rather than the 
1.19318 Mhz my PC hardware book claims.

All this tells me that I don't understand timer access in a modern 
system.  The code as written just dosen't seem like it would work on a 
4.77 Mhz XT.

> The resolution could be lowered.. Are there any writes to 0x40
> setting a divisor? If not, then the snippet will simply not be
> reliable down to the exact iteration.
> Since the code uses jb to detect when to stop looping the count
> doesn't have to be an exact match. Even if an extra tick passes,
> the loop will still end.

I don't understand.  The part I'm refering to is the

         sub     ax,dx
         neg     ax

	or	ax,ax
	jnz	delay_a

This will only skip the jump (and do the BX decrement) if ax is zero. 
For ax to be zero the result of the 2's complement subtraction must be 
zero or the when the 2 reads are the same number.  But I just don't see 
how this would happen repeatably at .6us per ISA IO.

Ate the timer reads really and ISA IO?  I guess if those reads are 
happening much faster then it would work.  Where does the timer live 
now? int the northbridge perhpas?  Thats could be the issue.  If the 
northbridge  responded to the IO it would happen at cpu clock rates and 
all would be well.

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