amd opteron dram controller

HC Wang hcwang at
Mon Apr 26 12:12:01 CEST 2004



I am working on post code for an embedded opteron board, I have some problem
with dram controller initialization, problem I have seen are (1) after
setting DramInit bit (bit 8) in dram configuration low register (bus 0, dev
24, func 2, reg 0x90), processor clear this bit after a while but DramEnable
(bit 10) and MemClrStatus (bit 11) never set high, is this a problem? If so
what is causing it? (2) After DramInit bit is cleared by processor, I can
access sdram from 0x00000000 to 0x0009ffff, fill it with pattern and verify
it.  But I can't write into address space from 0x000A0000 - 0x000EFFFF, even
MTRRs associated with it are set to UC type. Is this correct? (3) Can't
write memory above 1M (from 0x00100000 and up), but I can alter the memory
content by using AMD HDT..   Any ideas?





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