romcc fixes for AMD64

Eric W. Biederman ebiederman at lnxi.com
Tue Sep 16 13:26:01 CEST 2003


ron minnich <rminnich at lanl.gov> writes:

> On Tue, 16 Sep 2003, Stefan Reinauer wrote:
> 
> > This could be done using the Opterons PAE feature. Currently I see a
> > tradeoff between LinuxBIOS image size and the design conflict when going
> > away from 16bit firmware on 32bit systems while staying with 32bit on
> > a 64bit platform.
> 
> this won't last very long here. 36 bits only gets us to 64 GB -- too 
> small. 

PAE is really has 64bit addresses in the page tables.  Intel implements
36bits physical and AMD 40bits of physical address space.
 
> LinuxBIOS has run in 64-bit mode on a 64-bit platform -- the alpha. I see 
> no real issue with going to 64-bit opteron mode. 

Neither do I.  I have memory initialization working for all 64bits in 
32bit physical mode, so it isn't needed at the moment.  But there is
a noticeable performance hit.

Any dynamic page table based solution though needs to move out of
romcc compiled code, and into the normal part of LinuxBIOS where we
already have memory initialized.  That's not a bad idea anyway given
how slow it is to do memory writes over hypertransport before the link
speed is configured up.

> rno

Eric



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