[COMMIT] Infrastructure Updates 4

YhLu YhLu at tyan.com
Thu Sep 11 12:33:00 CEST 2003


It is AMD-8111 LPC, and 0x47 will trigger SWRST. I have checked the
schematic that pin is routed to corresponding LDT_RESET.

But it's no luck.

PCI: 01:04.0 [1022/7468] bus ops
PCI: 01:04.0 [1022/7468] enabled

  Bus  1, device   4, function  0:
    ISA bridge: Advanced Micro Devices [AMD] AMD-8111 LPC (rev 5).

-----邮件原件-----
发件人: Stefan Reinauer [mailto:stepan at suse.de] 
发送时间: 2003年9月11日 5:05
收件人: ron minnich
抄送: YhLu; ebiederman at lnxi.com; LinuxBIOS
主题: Re: [COMMIT] Infrastructure Updates 4

* ron minnich <rminnich at lanl.gov> [030908 17:03]:
> On Mon, 8 Sep 2003, Stefan Reinauer wrote:
> 
> > Did you have a look at the implementation of hard_reset in reset.c?
> > void hard_reset(void)
> > {
> >         set_bios_reset();
> >         pci_write_config8(PCI_DEV(1, 0x04, 0), 0x47, 1);
> > }
> 
> the only reset.c I see is in the mainboard-specific code. Nevertheless 
> this code really should do the find_device thing. 

I don't think that the wrong device is used though:
01:04.0 PCI bridge: Advanced Micro Devices [AMD] AMD-8111 PCI (rev 07)
PCI: 01:04.0 [1022/7460] enabled


Stefan




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