newer solo motherboards

Stefan Reinauer stepan at suse.de
Mon Sep 8 14:59:00 CEST 2003


* YhLu <YhLu at tyan.com> [030908 18:55]:
> HyperT reset needed
> HyperT reset not needed
> 
> In the scan_hypertranport_chain.c missed one "else"
> 
> YH.

./src/devices/hypertransport.c:hypertransport_scan_chain()
should do the right thing, i.e. trigger a reset. And it seems
the reset should go to PCIDEV(1,4,0), as on all other hammer boards.
But obviously the code does not do a reset, or does it continue at the
same PC afterwards?

> SMBus controller enabled
> Ram1.00
> setting up CPU00 northbridge registers
> done.
> Ram2.00

How can i verify that the smbus channels LinuxBIOS uses are correct for
my board? The old solos only found RAM in the first socket it seems.

> Hyper transport scan link: 0 max: 1
> PCI: 01:01.0 [1022/7454] enabled next_unitid: 0004
> PCI: 01:04.0 [1022/7460] enabled next_unitid: 0008
> HyperT reset needed
[ LinuxBIOS should restart HERE ]
> HyperT reset not needed
> PCI: pci_scan_bus for bus 1
> PCI: 01:01.0 [1022/7454] ops
[..]

  Stefan
-- 
Architecture Team
    SuSE Linux AG



More information about the coreboot mailing list