R: [COMMIT] freebios2 How much have I broken?

YhLu YhLu at tyan.com
Mon Oct 13 18:24:01 CEST 2003 

Eric,

I have tested it in Tyan S2885. The S2885 HT conf is
	
	8151
	|
	|<--- Link 0
	CPU0----CPU1
	|<--- Link 2
	|
	8131
	|
	|
	8111

the Config.lb define are:

northbridge amd/amdk8 "mc0"
        pci 0:18.0
        pci 0:18.0
        pci 0:18.0
        pci 0:18.1
        pci 0:18.2
        pci 0:18.3
        southbridge amd/amd8131 "amd8131" link 2
                pci 0:0.0
                pci 0:0.1
                pci 0:1.0
                pci 0:1.1
	end
	southbridge amd/amd8111 "amd8111" link 2
       	       	pci 0:0.0
	       	pci 0:1.0 on
	        pci 0:1.1 on
	        pci 0:1.2 on
	        pci 0:1.3 on
	        pci 0:1.5 on  <--- Enable Audio
	        pci 0:1.6 off
                pci 1:0.0 on
                pci 1:0.1 on
                pci 1:0.2 on
                pci 1:1.0 off
 
	end
        southbridge amd/amd8151 "amd8151" link 0
                pci 0:0.0
                pci 0:1.0
        end
end


The result for LinuxBIOS PCI allocation will be:

Finding PCI configuration type.
PCI: Using configuration type 1
Enumerating: AMD K8 Northbridge
Enumerating: AMD K8 Northbridge
Enumerating: AMD K8
Enumerating: AMD K8
Enumerating: AMD 8111
Enumerating buses...PCI: pci_scan_bus for bus 0
PCI: 00:18.0 [1022/1100] enabled
PCI: 00:18.1 [1022/1101] enabled
PCI: 00:18.2 [1022/1102] enabled
PCI: 00:18.3 [1022/1103] ops
PCI: 00:18.3 [1022/1103] enabled
PCI: 00:19.0 [1022/1100] enabled
PCI: 00:19.1 [1022/1101] enabled
PCI: 00:19.2 [1022/1102] enabled
PCI: 00:19.3 [1022/1103] ops
PCI: 00:19.3 [1022/1103] enabled
amdk8_scan_chains max: 0 starting...
Hyper transport scan link: 0 max: 1
Missing static device: PCI: 01:00.0
PCI: pci_scan_bus for bus 1
PCI: 01:00.0 [ffff/ffff/00ffff] has unknown header type ff, ignoring.
PCI: 01:00.0 No device operations
PCI: 01:01.0 [ffff/ffff/00ffff] has unknown header type ff, ignoring.
PCI: 01:01.0 No device operations
PCI: pci_scan_bus returning with max=01
Hyper transport scan link: 0 new max: 1
Hypertransport scan link done
Hyper transport scan link: 2 max: 2
PCI: 02:01.0 [1022/7450] enabled next_unitid: 0003
PCI: 02:03.0 [1022/7460] enabled next_unitid: 0007
PCI: pci_scan_bus for bus 2
PCI: 02:01.0 [1022/7450] bus ops
PCI: 02:01.0 [1022/7450] enabled
PCI: 02:01.1 [1022/7451] ops
PCI: 02:01.1 [1022/7451] enabled
PCI: 02:02.0 [1022/7450] bus ops
PCI: 02:02.0 [1022/7450] enabled
PCI: 02:02.1 [1022/7451] ops
PCI: 02:02.1 [1022/7451] enabled
PCI: 02:03.0 [1022/7460] enabled
PCI: 02:04.0 [1022/7468] bus ops
PCI: 02:04.0 [1022/7468] enabled
PCI: 02:04.1 [1022/7469] ops
PCI: 02:04.1 [1022/7469] enabled
PCI: 02:04.2 [1022/746a] enabled
PCI: 02:04.3 [1022/746b] ops
PCI: 02:04.3 [1022/746b] enabled
PCI: 02:04.5 [1022/746d] enabled
amd8111_enable dev: PCI: 02:04.6 lpc_dev: PCI: 02:04.0 index: 6 reg: ffff ->
ffbf done
PCI: 02:04.6 [ffff/ffff] disabled
PCI: pci_scan_bus for bus 3
PCI: 03:09.0 [14e4/16a7] ops
PCI: 03:09.0 [14e4/16a7] enabled
PCI: pci_scan_bus returning with max=03
PCI: pci_scan_bus for bus 4
PCI: pci_scan_bus returning with max=04
PCI: pci_scan_bus for bus 5
PCI: 05:00.0 [1022/7464] ops
PCI: 05:00.0 [1022/7464] enabled
PCI: 05:00.1 [1022/7464] ops
PCI: 05:00.1 [1022/7464] enabled
PCI: 05:00.2 [1022/7463] ops
PCI: 05:00.2 [1022/7463] enabled
amd8111_enable dev: PCI: 05:01.0 lpc_dev: PCI: 02:04.0 index: 9 reg: ffbf ->
fdbf done
PCI: 05:01.0 [ffff/ffff] disabled
PCI: 05:0b.0 [1095/3114] ops
PCI: 05:0b.0 [1095/3114] enabled
PCI: 05:0c.0 [104c/8023] ops
PCI: 05:0c.0 [104c/8023] enabled
PCI: pci_scan_bus returning with max=05
PCI: pci_scan_bus returning with max=05
Hyper transport scan link: 2 new max: 5
Hypertransport scan link done
amdk8_scan_chains max: 5 done
amdk8_scan_chains max: 5 starting...
amdk8_scan_chains max: 5 done
PCI: pci_scan_bus returning with max=05
Done

It scaned 8151 at first and 8131/8111. But it can not enable 8151.

In the src/northbridge/amd/amdk8/northbridge.c. I changed the scan sequence
from to 2 to 0. then I got

Finding PCI configuration type.
PCI: Using configuration type 1
Enumerating: AMD K8 Northbridge
Enumerating: AMD K8 Northbridge
Enumerating: AMD K8
Enumerating: AMD K8
Enumerating: AMD 8111
Enumerating buses...PCI: pci_scan_bus for bus 0
PCI: 00:18.0 [1022/1100] enabled
PCI: 00:18.1 [1022/1101] enabled
PCI: 00:18.2 [1022/1102] enabled
PCI: 00:18.3 [1022/1103] ops
PCI: 00:18.3 [1022/1103] enabled
PCI: 00:19.0 [1022/1100] enabled
PCI: 00:19.1 [1022/1101] enabled
PCI: 00:19.2 [1022/1102] enabled
PCI: 00:19.3 [1022/1103] ops
PCI: 00:19.3 [1022/1103] enabled
amdk8_scan_chains max: 0 starting...
Hyper transport scan link: 2 max: 1
PCI: 01:01.0 [1022/7450] enabled next_unitid: 0003
PCI: 01:03.0 [1022/7460] enabled next_unitid: 0007
PCI: pci_scan_bus for bus 1
PCI: 01:01.0 [1022/7450] bus ops
PCI: 01:01.0 [1022/7450] enabled
PCI: 01:01.1 [1022/7451] ops
PCI: 01:01.1 [1022/7451] enabled
PCI: 01:02.0 [1022/7450] bus ops
PCI: 01:02.0 [1022/7450] enabled
PCI: 01:02.1 [1022/7451] ops
PCI: 01:02.1 [1022/7451] enabled
PCI: 01:03.0 [1022/7460] enabled
PCI: 01:04.0 [1022/7468] bus ops
PCI: 01:04.0 [1022/7468] enabled
PCI: 01:04.1 [1022/7469] ops
PCI: 01:04.1 [1022/7469] enabled
PCI: 01:04.2 [1022/746a] enabled
PCI: 01:04.3 [1022/746b] ops
PCI: 01:04.3 [1022/746b] enabled
PCI: 01:04.5 [1022/746d] enabled
amd8111_enable dev: PCI: 01:04.6 lpc_dev: PCI: 01:04.0 index: 6 reg: ffff ->
ffbf done
PCI: 01:04.6 [ffff/ffff] disabled
PCI: pci_scan_bus for bus 2
PCI: 02:09.0 [14e4/16a7] ops
PCI: 02:09.0 [14e4/16a7] enabled
PCI: pci_scan_bus returning with max=02
PCI: pci_scan_bus for bus 3
PCI: pci_scan_bus returning with max=03
PCI: pci_scan_bus for bus 4
PCI: 04:00.0 [1022/7464] ops
PCI: 04:00.0 [1022/7464] enabled
PCI: 04:00.1 [1022/7464] ops
PCI: 04:00.1 [1022/7464] enabled
PCI: 04:00.2 [1022/7463] ops
PCI: 04:00.2 [1022/7463] enabled
amd8111_enable dev: PCI: 04:01.0 lpc_dev: PCI: 01:04.0 index: 9 reg: ffbf ->
fdbf done
PCI: 04:01.0 [ffff/ffff] disabled
PCI: 04:0b.0 [1095/3114] ops
PCI: 04:0b.0 [1095/3114] enabled
PCI: 04:0c.0 [104c/8023] ops
PCI: 04:0c.0 [104c/8023] enabled
PCI: pci_scan_bus returning with max=04
PCI: pci_scan_bus returning with max=04
Hyper transport scan link: 2 new max: 4
Hypertransport scan link done
Hyper transport scan link: 0 max: 5
PCI: 05:01.0 [1022/7454] enabled next_unitid: 0004
PCI: pci_scan_bus for bus 5
PCI: 05:01.0 [1022/7454] ops
PCI: 05:01.0 [1022/7454] enabled
PCI: 05:02.0 [1022/7455] bus ops
PCI: 05:02.0 [1022/7455] enabled
PCI: pci_scan_bus for bus 6
PCI: pci_scan_bus returning with max=06
PCI: pci_scan_bus returning with max=06
Hyper transport scan link: 0 new max: 6
Hypertransport scan link done
amdk8_scan_chains max: 6 done
amdk8_scan_chains max: 6 starting...
amdk8_scan_chains max: 6 done
PCI: pci_scan_bus returning with max=06
Done


So it seems that 8131/8111 should be enumerated before 8151 at last.

I suggest you add support to reverse scan.

        southbridge amd/amd8131 "amd8131" scan 0 link 2 
        southbridge amd/amd8151 "amd8151" scan 1 link 0

Regards

Yinghai Lu


-----邮件原件-----
发件人: ebiederman at lnxi.com [mailto:ebiederman at lnxi.com] 
发送时间: 2003年10月10日 23:39
收件人: LinuxBIOS
主题: [COMMIT] freebios2 How much have I broken?


This is a flush of all my pending Opteron bug fixes.
Plus a new version of romcc, with all of the outstanding changes.
Plus some very recent work on getting enables and disables of devices
  working properly.
Plus my reindenting/beautify tirad on the via epia code.

The guts look good but I suspect I have introduced some problems with
ports other than the hdama.  Especially with the configuration updates.
My apologies for not looking those up and fixing them but I need to go home,
and my queue of pending changes is far to long already.

Eric

- 1.1.5
  - O2, enums, and switch statements work in romcc
  - Support for compiling romcc on non x86 platforms
  - new romc options -msse and -mmmx for specifying extra registers to use
  - Bug fixes to device the device disable/enable framework and an amd8111
implementation
  - Move the link specification to the chip specification instead of the
path
  - Allow specifying devices with internal bridges.
  - Initial via epia support
  - Opteron errata fixes

VS: ----------------------------------------------------------------------
CVS: Enter Log.  Lines beginning with `CVS:' are removed automatically
CVS:
CVS: Committing in .
CVS:
CVS: Modified Files:
CVS:    NEWS src/arch/i386/config/make.base
CVS:    src/arch/i386/lib/console.inc src/arch/i386/lib/cpu.c
CVS:    src/boot/hardwaremain.c src/config/Config src/config/Config.lb
CVS:    src/config/Options.lb src/cpu/k8/cpufixup.c src/cpu/p6/mtrr.c
CVS:    src/devices/chip.c src/devices/device.c
CVS:    src/devices/device_util.c src/devices/hypertransport.c
CVS:    src/devices/pci_device.c src/devices/root_device.c
CVS:    src/include/cpu/k8/mtrr.h src/include/device/chip.h
CVS:    src/include/device/device.h src/include/device/path.h
CVS:    src/mainboard/amd/quartet/mptable.c
CVS:    src/mainboard/arima/hdama/Config
CVS:    src/mainboard/arima/hdama/Config.lb
CVS:    src/mainboard/arima/hdama/auto.c
CVS:    src/mainboard/arima/hdama/failover.c
CVS:    src/mainboard/arima/hdama/irq_tables.c
CVS:    src/mainboard/arima/hdama/mainboard.c
CVS:    src/mainboard/arima/hdama/mptable.c
CVS:    src/northbridge/amd/amdk8/Config
CVS:    src/northbridge/amd/amdk8/Config.lb
CVS:    src/northbridge/amd/amdk8/coherent_ht.c
CVS:    src/northbridge/amd/amdk8/misc_control.c
CVS:    src/northbridge/amd/amdk8/northbridge.c
CVS:    src/northbridge/amd/amdk8/raminit.c
CVS:    src/northbridge/via/vt8601/northbridge.c src/pc80/vgabios.c
CVS:    src/pc80/vgachip.h src/southbridge/amd/amd8111/Config.lb
CVS:    src/southbridge/amd/amd8111/amd8111_acpi.c
CVS:    src/southbridge/amd/amd8111/amd8111_early_smbus.c
CVS:    src/southbridge/amd/amd8111/amd8111_ide.c
CVS:    src/southbridge/amd/amd8111/amd8111_lpc.c
CVS:    src/southbridge/amd/amd8111/amd8111_usb.c
CVS:    src/southbridge/amd/amd8111/amd8111_usb2.c
CVS:    src/southbridge/amd/amd8131/amd8131_bridge.c
CVS:    src/southbridge/via/vt8231/chip.h
CVS:    src/southbridge/via/vt8231/vt8231.c
CVS:    src/southbridge/via/vt8231/vt8231_early_serial.c
CVS:    src/southbridge/via/vt8231/vt8231_early_smbus.c
CVS:    src/superio/NSC/pc87360/chip.h
CVS:    src/superio/NSC/pc87360/superio.c targets/buildtarget
CVS:    targets/arima/hdama/Config.lb util/newconfig/Makefile
CVS:    util/newconfig/config.g util/options/build_opt_tbl.c
CVS:    util/romcc/Makefile util/romcc/romcc.c
CVS:    util/romcc/tests/simple_test60.c
CVS: Added Files:
CVS:    src/northbridge/amd/amdk8/cpu_rev.c
CVS:    src/northbridge/amd/amdk8/mcf0_control.c
CVS:    src/southbridge/amd/amd8111/amd8111.c
CVS:    src/southbridge/amd/amd8111/amd8111.h
CVS:    src/southbridge/amd/amd8111/amd8111_ac97.c
CVS:    src/southbridge/amd/amd8111/amd8111_nic.c
CVS:    util/romcc/results/linux_test1.out
CVS:    util/romcc/results/linux_test2.out
CVS:    util/romcc/results/linux_test3.out
CVS:    util/romcc/results/linux_test4.out
CVS:    util/romcc/results/linux_test5.out
CVS:    util/romcc/results/linux_test6.out
CVS:    util/romcc/results/linux_test7.out
CVS:    util/romcc/tests/fail_test4.c util/romcc/tests/fail_test5.c
CVS:    util/romcc/tests/linux_console.h
CVS:    util/romcc/tests/linux_syscall.h
CVS:    util/romcc/tests/linux_test1.c util/romcc/tests/linux_test2.c
CVS:    util/romcc/tests/linux_test3.c util/romcc/tests/linux_test4.c
CVS:    util/romcc/tests/linux_test5.c util/romcc/tests/linux_test6.c
CVS:    util/romcc/tests/linux_test7.c
CVS:    util/romcc/tests/linuxi386_syscall.h
CVS:    util/romcc/tests/raminit_test6.c
CVS:    util/romcc/tests/simple_test57.c
CVS:    util/romcc/tests/simple_test58.c
CVS:    util/romcc/tests/simple_test61.c
CVS:    util/romcc/tests/simple_test62.c
CVS:    util/romcc/tests/simple_test63.c
CVS:    util/romcc/tests/simple_test64.c
CVS:    util/romcc/tests/simple_test65.c
CVS:    util/romcc/tests/simple_test66.c
CVS:    util/romcc/tests/simple_test67.c
CVS:    util/romcc/tests/simple_test68.c
CVS: ----------------------------------------------------------------------
_______________________________________________
Linuxbios mailing list
Linuxbios at clustermatic.org
http://www.clustermatic.org/mailman/listinfo/linuxbios

-------------- next part --------------
An embedded and charset-unspecified text was scrubbed...
Name: S2885_new_reverse_scan_without_Hardreset_OK_2.txt
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20031013/36cf2e57/attachment.txt>
-------------- next part --------------
An embedded and charset-unspecified text was scrubbed...
Name: S2885_new_normal_scan_without_Hardreset_2.txt
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20031013/36cf2e57/attachment-0001.txt>

More information about the coreboot mailing list