V2 EPIA: success

SONE Takeshi ts1 at tsn.or.jp
Thu Oct 2 14:51:01 CEST 2003


On Thu, Oct 02, 2003 at 12:17:57PM -0600, ron minnich wrote:
> 
> Linux is now up. Tweak this, tweak that in southbridge and at some point 
> it works. Looks like we needed some ISA config to make it go.
> 
> So V2 is up on the EPIA. Now if we can all come to closure on the config 
> tool we'll be getting there :-)
> 
> This afternoon I will try to get the memory system to be sane.
> 
> Wow, this is fun, these little EPIAs are great cluster nodes. Small box, 
> wrapped in steel so I can't break anything, powered by a wall wart. I love 
> 'em.

Congrats, and thank you very much for the work!

If you don't know it yet, this might help debugging SPD stuff..
I just found a tool in lm-sensors, which decodes SPD bytes.


black:/usr/src/modules/lm-sensors/prog/eeprom$ ./decode-dimms.pl 


PC DIMM Serial Presence Detect Tester/Decoder
Written by Philip Edelbrock.  Copyright 1998, 1999.
Modified by Christian Zuckschwerdt <zany at triq.net>
Version 2.6.3

Decoding EEPROM	/proc/sys/dev/sensors/eeprom-i2c-1-50
Guessing DIMM is in	bank 1

---=== The Following is Required Data and is Applicable to all DIMM Types ===---
# of bytes written to SDRAM EEPROM	128
Total number of bytes in EEPROM	256
Fundemental Memory type	SDRAM
Number of Row Address Bits (SDRAM only)	13
Number of Col Address Bits (SDRAM only)	10
Number of Module Rows	1
Data Width (SDRAM only)	64
Module Interface Signal Levels	LVTTL
Cycle Time (SDRAM) highest CAS latency	7.5ns
Access Time (SDRAM)	5.4ns
Module Configuration Type	No Parity
Refresh Type	Self Refreshing
Refresh Rate	Reduced (7.8uS)
Primary SDRAM Component Bank Config	No Bank2 OR Bank2 = Bank1 width
Primary SDRAM Component Widths	8
Error Checking SDRAM Component Bank Config	No Bank2 OR Bank2 = Bank1 width
Error Checking SDRAM Component Widths	Undefined!
Min Clock Delay for Back to Back Random Access	1

---=== The Following Apply to SDRAM DIMMs ONLY ===---
Burst lengths supported	Burst Length = 1
		Burst Length = 2
		Burst Length = 4
		Burst Length = 8
		Burst Length = Page
		
Number of Device Banks	4
Supported CAS Latencies	CAS Latency = 2
		CAS Latency = 3
		
Supported CS Latencies	CS Latency = 0
		
Supported WE Latencies	WE Latency = 0
		
SDRAM Module Attributes	(None Reported)
		
SDRAM Device Attributes (General)	Supports Auto-Precharge
		Supports Precharge All
		Supports Write1/Read Burst
		Lower VCC Tolerance:10%
		Upper VCC Tolerance:10%
		
SDRAM Cycle Time (2nd highest CAS)	7.5nS
SDRAM Access from Clock Time (2nd highest CAS)	5.4nS

---=== The Following are Optional (may be Bogus) ===---
SDRAM Cycle Time (3rd highest CAS)	Undefined!
SDRAM Access from Clock Time (3rd highest CAS)	Undefined!

---=== The Following are Required (for SDRAMs) ===---
Minumum Row Precharge Time	15nS
Row Active to Row Active Min	15nS
RAS to CAS Delay	15nS
Min RAS Pulse Width	37nS

---=== The Following are Required and Apply to ALL DIMMs ===---
Row Densities	256 MByte
		

---=== The Following are Proposed and Apply to SDRAM DIMMs ===---
Command and Address Signal Setup Time	1.5nS
Command and Address Signal Hold Time	0.8nS
Data Signal Setup Time	1.5nS
Data Signal Hold Time	0.8nS
SPD Revision code 	12
EEPROM Checksum of bytes 0-62	0x89 (verses calculated: 0x89)
		
Manufacturer's JEDEC ID Code	0x0000000000000000
		
Manufacturer's JEDEC ID Code	("        ")
Manufacturing Location Code	0x00
		
Manufacurer's Part Number:"	32MX64U-133 32MX8 
Revision Code	0x0000
		
Manufacturing Date	0x0000
		
Intel Specification for Frequency	100MHz
		
Intel Spec Details for 100MHz Support	CAS Latency = 2
		CAS Latency = 3
		Junction Temp B (100 degrees C)
		CLK 3 Connected
		CLK 2 Connected
		CLK 1 Connected
		CLK 0 Connected
		Double Sided DIMM
		
Number of SDRAM DIMMs detected and decoded	1

Try './decode-dimms.pl --format' for html output.
black:/usr/src/modules/lm-sensors/prog/eeprom$ 
-- 
Takeshi



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