question about amd8111_early_smbus.c

[ron minnich]

Here's some enable code

static void enable_smbus(void)
{
        device_t dev;
        dev = pci_locate_device(PCI_ID(0x1022, 0x746b), 0);
        if (dev == PCI_DEV_INVALID) {
                die("SMBUS controller not found\r\n");
        }
        uint8_t enable;
        print_debug("SMBus controller enabled\r\n");
        pci_write_config32(dev, 0x58, SMBUS_IO_BASE | 1);
        enable = pci_read_config8(dev, 0x41);
        pci_write_config8(dev, 0x41, enable | (1 << 7));
        /* clear any lingering errors, so the transaction will run */
        outw(inw(SMBUS_IO_BASE + SMBGSTATUS), SMBUS_IO_BASE + SMBGSTATUS);
}


Sounds OK, right? here's what I don't get:

#define SMBUS_IO_BASE 0x0f00

#define SMBGSTATUS 0xe0
#define SMBGCTL    0xe2
#define SMBHSTADDR 0xe4

etc.etc.

The io base is f00. The SMB registers get added to that: you get fe0, etc. 

I can interpret this two ways, one of them being that the IOBASE is fe0, 
and the way this is written is to optimize romcc behavior. But then I 
don't get this part:
        pci_write_config32(dev, 0x58, SMBUS_IO_BASE | 1);

I would expect this to be set to SUMBUS_IO_BASE|0xE0|1 so that that the 
IOBASE in the register is 0xfe0. 

Or something else is going on here and I am *really* lost. Somebody want 
to clear my confusion :-)

ron