Level 2 cache activation code?

[Svante Signell]

I still do get a segfault when trying to activate the L2 cache, in the
cache_enable() inline assembly routine in l2_cache.c Anything else
neeeded to run this program inside GNU/Linux 

On Fri, 2003-11-07 at 15:42, steven james wrote:
> Greetings,
> 
> Yes, anything non 0 is true. Testing that way (or if(res<0) when the
> function is to return a count) generally helps to catch wierdness (in the
> bad old days, some functions returned -errno or even errno on error but
> always 0 on success, this catches all of those cases).
> 
> G'day,
> sjames
> 
> 
> On Thu, 2003-11-06 at 14:59, steven james wrote:
> > Greetings,
> > 
> > To run that code inside linux, you need to add a call to iopl to
allow
> > direct hardware access like:
> > 
> > res = iopl(3);
> > if(res) {
> >     report_error();
> >     exit(-1);
> > }
> > 
> > or something to that effect.
> > G'day,
> > sjames
> > 
> On Fri, 7 Nov 2003, Svante Signell wrote:
> 
> > Steven,
> > 
> > Thanks for the tip, I'll try adding this in. Preliminary estimations
> > with lmbench-2.0 shows like the problems are probably due to the missing
> > L2 cache. I'm currently compiling and running running lmbench-3, but
> > with an efficient speed of 7MHz instead of 1300MHz, things take time...
> > 
...
> > > > 5. If the slowness is not due to a disabled L2 cache (how to test this
> > > > properly btw?), can the  problems be solved by tying with the mtrr or
> > > > microcode update code? 
> > > > 
> > > > 6. Maybe the problem is still hardware related, like the on-board
> > > > voltage regulator for the CPU is not working properly, even if there are
> > > > no indications at all from the on board sensors. However, if the
> > > > problems are software related and can be solved, do you think it is
> > > > feasible to replace the AMI BIOS with LinuxBIOS? The probability of
> > > > getting an updated BIOS from MSI supporting Coppermine and Tualatin
> > > > processors is probably zero.
> > > > 
> > > > Thanks,
> > > > Svante 
> >