Level 2 cache activation code?

Svante Signell svante.signell at telia.com
Thu Nov 6 17:55:01 CET 2003


On Thu, 2003-11-06 at 15:11, ron minnich wrote:
> On Thu, 6 Nov 2003, Svante Signell wrote:
> 
> > Sorry for taking up this thread again but now I have made a test of the
> > l2_cache activation code and have some further questions. 
> 
> you don't need this code any more. The last processor it mattered for is 
> long dead. I am not removing it but if you are having trouble then you 
> have a PII; do you?

No, I have a Pentium 2 1.3GHz Tualatin processor that works properly on other 
440BX-based main boards such as QDI BrillianX 1 and Compaq Presario 5670. I'm 
using a slot 1 to socket 370 converter, SLOT-T from Upgradeware for this CPU.
  
BTW: What do you mean by PIIs are long dead? I think _many_ people are
still using PIIs, especially with 400BX-based main boards. What I have
done is to extend the life of my old computers and their main boards by
exchanging the PIIs with PIIIs, specifically using Celeron2, with 1.4
GHz frequency (or 1.3GHz, since 1.4GHz versions are hard to find
currently).

Intel is phasing out these Celeron2s today, but compatible CPUs with
decent performance and clock frequencies are becoming available, e.g.
the VIA C3 Nehemiah, today at 1.2GHz. Versions up to 2GHz are coming
soon. Even SMP capable processors are in this years roadmap. Now we are
talking low power and cheap solutions (and maybe even fan-less). I plan
to use SMP-able processors from VIA for my currently problematic
motherboard when available.  The first step is to make things run with
one CPU. 

The motherboard is a dual CPU MSI-6120 with built-in SCSI interfaces. It
is currently equipped with two SMP-able PII-type Celerons (Mendocino)
300MHz at 468MHz. This motherboard have been working properly for four
years now and it would (in my opinion) be a big waste to throw it away.
I even consider to replace the problematic BIOS with a LinuxBIOS if the
problem is found not to be hardware related.

> > 4. You state that the L2 cache stuff is only needed for P2 CPUs, not for
> > P3 type CPUs, such as Coppermine or Tualatin. I'm testing with a Celeron
> > 2 CPU (Tualatin), which is of P3 type. What if the BIOS does not
> > recognise the CPU and disables the L2 cache? People claim that AMI
> > BIOSes work this way. It the enabling code sufficient to make things
> > work.
> 
> which BIOS?

The BIOS is from AMI with version 2.0 (a6120v20.exe) supplied by MSI.

> > 5. If the slowness is not due to a disabled L2 cache (how to test this
> > properly btw?), can the  problems be solved by tying with the mtrr or
> > microcode update code? 
> 
> use lmbench to scope out your caches.

OK, I have now run lmbench on two boxes, one QDI box with a 1.4GHz
Celeron2 and the MSI-6120 with a 1.3GHz Celeron2, both with SLOT-T
adapters. How to find out where the bottleneck is, especially if the L2
cache is enabled or not? A lot of data is written on the log files. I'm
currently trying to find out what all numbers mean. One quick
observation though, the correctly working box is reported as: MHZ: 1409
MHz, 0.71 nanosec clock, while the problematic one is reported as: MHZ:
7 MHz, 142.86 nanosec clock. A factor of 200 in slowdown, welcome back
to the old 8086 clock speeds ;-)

> ron

Thanks,
Svante



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