EPIA VGA patch

SONE Takeshi ts1 at cma.co.jp
Wed May 14 04:03:01 CEST 2003


Hello,
I started with a fresh checkout of CVS tree (since my current working tree
is a mess) and made a minimum modification to boot ADLO with VGA BIOS
to enable video on a EPIA.

With attached patches, my EPIA 5000 boots into GRUB (then Linux)
with VGA console.

lb-epia.patch
    This applies to LinuxBIOS itself.
    Enables shadow RAM, adds vgainit.inc (it is harmless unless
    HAVE_FRAMEBUFFER is enabled), and a minimum fix to raminit.inc.
    Ron, please apply this one.

adlo-epia.patch
    This is for ADLO.
    Since it includes changes specific to EPIA, it should not (entirely) 
    go into CVS.
    Note that this includes serial debug patch by hcyun, and EPIA
    doesn't work without it. Perhaps a timing problem?

pirq-EPIA.bin
    This should be put at util/ADLO/pirq.
    It was taken from LinuxBIOS, not Award BIOS (I think it makes sense).
    Of cource, VGA BIOS is also required and it must be taken from your box.

As I said this is minimum modification, it does not boot very fast,
and it may fail to detect IDE at cold boot.
For these issues, I have already posted fixes to the list.

RAM is fixed at 64MB, as current CVS is.
If you change this, you have to hack raminit.inc, as well as CMOS value
in the ADLO/loader.s.
I'm working on automatic detection of RAM.

Have fun.
-- 
Takeshi
-------------- next part --------------
diff -urN freebios-cvs/src/mainboard/via/epia/Config freebios-vga/src/mainboard/via/epia/Config
--- freebios-cvs/src/mainboard/via/epia/Config	2002-12-14 15:34:34.000000000 +0900
+++ freebios-vga/src/mainboard/via/epia/Config	2003-05-14 04:10:50.000000000 +0900
@@ -11,6 +11,7 @@
 mainboardinit pc80/serial.inc
 mainboardinit arch/i386/lib/console.inc
 mainboardinit northbridge/via/vt8601/raminit.inc
+mainboardinit northbridge/via/vt8601/vgainit.inc
 mainboardinit southbridge/via/vt8231/ideconfig.inc
 # mainboardinit ram/dump_northbridge.inc
 # mainboardinit ram/ramtest.inc
diff -urN freebios-cvs/src/northbridge/via/vt8601/northbridge.c freebios-vga/src/northbridge/via/vt8601/northbridge.c
--- freebios-cvs/src/northbridge/via/vt8601/northbridge.c	2003-05-13 22:13:51.000000000 +0900
+++ freebios-vga/src/northbridge/via/vt8601/northbridge.c	2003-05-14 16:41:52.000000000 +0900
@@ -19,6 +19,15 @@
 
 	if (! pcidev)
 		return 0;
+
+	/* Turn on shadow DRAM at 0xC0000-0xFFFFF so we can write
+	 * PIRQ table, VGA BIOS, Bochs BIOS, etc.
+	 * -- ts1 05/14/03 */
+	printk_debug("Enabling shadow DRAM at 0xC0000-0xFFFFF: ");
+	pci_write_config_byte(pcidev, 0x61, 0xff);
+	pci_write_config_byte(pcidev, 0x62, 0xff);
+	pci_write_config_byte(pcidev, 0x63, 0xf0);
+	printk_debug("done\n");
 	
 	// Documentation on VT8601 - Pg 51 Rev 1.3 Sept 1999 says
 	// Device 0 Offset FB - Frame buffer control
@@ -69,7 +78,7 @@
 	static struct mem_range mem[3];
 	mem[0].basek = 0;
 	mem[0].sizek = 640;
-	mem[1].basek = 1024;
+	mem[1].basek = 768;
 	mem[1].sizek = __sizeram();
 	mem[2].basek = 0;
 	mem[2].sizek = 0;
diff -urN freebios-cvs/src/northbridge/via/vt8601/raminit.inc freebios-vga/src/northbridge/via/vt8601/raminit.inc
--- freebios-cvs/src/northbridge/via/vt8601/raminit.inc	2003-05-14 03:49:33.000000000 +0900
+++ freebios-vga/src/northbridge/via/vt8601/raminit.inc	2003-05-14 03:50:41.000000000 +0900
@@ -175,7 +175,7 @@
 		helped a tiny bit. We can get to schedule() before we crash, but only
 		if we set a breakpoint after the first loop in free_all_bootmem_core
  */
-        CS_WRITE($0x56, $0x10)
-        CS_WRITE($0x57, $0x10)
+        CS_WRITE($0x56, $0x08)
+        CS_WRITE($0x57, $0x08)
 
 	intel_chip_post_macro(0x36)
diff -urN freebios-cvs/src/northbridge/via/vt8601/vgainit.inc freebios-vga/src/northbridge/via/vt8601/vgainit.inc
--- freebios-cvs/src/northbridge/via/vt8601/vgainit.inc	1970-01-01 09:00:00.000000000 +0900
+++ freebios-vga/src/northbridge/via/vt8601/vgainit.inc	2003-05-14 03:51:56.000000000 +0900
@@ -0,0 +1,22 @@
+#if HAVE_FRAMEBUFFER
+
+/* Frame buffer size in MBytes */
+#ifndef SMA_SIZE
+#define SMA_SIZE 8
+#endif
+
+#if SMA_SIZE==2
+#define FBREG 0x90
+#elif SMA_SIZE==4
+#define FBREG 0xa0
+#elif SMA_SIZE==8
+#define FBREG 0xb0
+#else
+#error SMA_SIZE should be 2, 4, or 8 (MB)
+#endif
+
+	CS_WRITE($0xf8, $0x22) // DRAM arbitation timer - AGP, Host
+	CS_WRITE($0xf9, $0x42) // DRAM arbitation timer - VGA priority, normal
+	CS_WRITE($0xfb, $FBREG) // VGA enable
+
+#endif
-------------- next part --------------
diff -urN freebios-cvs/util/ADLO/Makefile freebios-vga/util/ADLO/Makefile
--- freebios-cvs/util/ADLO/Makefile	2002-11-25 11:07:53.000000000 +0900
+++ freebios-vga/util/ADLO/Makefile	2003-05-14 03:58:24.000000000 +0900
@@ -12,6 +12,7 @@
 PIRQ_M=pirq/pirq-MS7308E.bin
 PIRQ_P=pirq/pirq-P6STMT.bin
 PIRQ_T=pirq/pirq-ThinkPad.T23.bin
+PIRQ_EPIA=pirq/pirq-EPIA.bin
 
 BOCHS_R=bochs
 BOCHS_B=bochs/bios
@@ -25,6 +26,7 @@
 VIDEO64W=video/video.bios-WINFAST64kb.bin
 VIDEO64M=
 VIDEO64P=video/video.bios-P6STMT-64kb.bin
+VIDEO64EPIA=video/video.bios-EPIA-64kb.bin
 
 PAYLOAD=payload
 
@@ -37,7 +39,7 @@
 #-------------------------------------------------
 
 build: loader.o bios
-	cat ${ELF129} ${LOADER} ${PIRQ_M} ${BIOS_B} ${VIDEO64P} > ${PAYLOAD}
+	cat ${ELF129} ${LOADER} ${PIRQ_EPIA} ${BIOS_B} ${VIDEO64EPIA} > ${PAYLOAD}
 
 #-------------------------------------------------
 
Binary files freebios-cvs/util/ADLO/bochs/bios/rombios.bin and freebios-vga/util/ADLO/bochs/bios/rombios.bin differ
diff -urN freebios-cvs/util/ADLO/bochs/bios/rombios.c freebios-vga/util/ADLO/bochs/bios/rombios.c
--- freebios-cvs/util/ADLO/bochs/bios/rombios.c	2002-11-25 11:07:53.000000000 +0900
+++ freebios-vga/util/ADLO/bochs/bios/rombios.c	2003-05-14 04:34:10.000000000 +0900
@@ -1424,18 +1424,78 @@
   pop  bp
   ASM_END
 }
- 
-  void
+
+#define SERIAL_DEBUG
+
+#ifdef SERIAL_DEBUG
+
+/* Data */
+#define UART_RBR 0x00
+#define UART_TBR 0x00
+
+/* Control */
+#define UART_IER 0x01
+#define UART_IIR 0x02
+#define UART_FCR 0x02
+#define UART_LCR 0x03
+#define UART_MCR 0x04
+#define UART_DLL 0x00
+#define UART_DLM 0x01
+
+/* Status */
+#define UART_LSR 0x05
+#define UART_MSR 0x06
+#define UART_SCR 0x07
+
+int uart_can_tx_byte(base_port)
+     Bit16u base_port; 
+{
+	return inb(base_port + UART_LSR) & 0x20;
+}
+
+void uart_wait_to_tx_byte(base_port)
+     Bit16u base_port;      
+{
+	while(!uart_can_tx_byte(base_port))
+		;
+}
+
+void uart_wait_until_sent(base_port)
+     Bit16u base_port;      
+{
+	while(!(inb(base_port + UART_LSR) & 0x40)) 
+		;
+}
+
+void uart_tx_byte(base_port, data)
+     Bit16u base_port; 
+     Bit8u  data;      
+{
+  uart_wait_to_tx_byte(base_port);
+  outb(base_port + UART_TBR, data);
+  /* Make certain the data clears the fifos */
+  uart_wait_until_sent(base_port);
+}
+
+#endif 
+
+void
 send(action, c)
   Bit16u action;
   Bit8u  c;
 {
+
+#ifdef SERIAL_DEBUG // hcyun
+  if ( c == '\n') uart_tx_byte(0x3f8, '\r'); 
+  uart_tx_byte(0x3f8, c);
+#else
   if (action & BIOS_PRINTF_DEBUG) outb(DEBUG_PORT, c);
   if (action & BIOS_PRINTF_INFO) outb(INFO_PORT, c);
   if (action & BIOS_PRINTF_SCREEN) {
     if (c == '\n') wrch('\r');
     wrch(c);
-    }
+  }
+#endif 
 }
 
   void
Binary files freebios-cvs/util/ADLO/loader.o and freebios-vga/util/ADLO/loader.o differ
diff -urN freebios-cvs/util/ADLO/loader.s freebios-vga/util/ADLO/loader.s
--- freebios-cvs/util/ADLO/loader.s	2002-11-25 11:07:53.000000000 +0900
+++ freebios-vga/util/ADLO/loader.s	2003-05-14 14:39:05.000000000 +0900
@@ -50,13 +50,13 @@
 ;*****************************************************
 ; B) shadow - ON (enable/read/write)
 
-mov eax, #0x80000070
-mov dx,  #0x0cf8
-out dx,  eax
-
-mov eax, #0xFFFFFFFF
-mov dx,  #0x0cfc
-out dx,  eax
+;mov eax, #0x80000070
+;mov dx,  #0x0cf8
+;out dx,  eax
+;
+;mov eax, #0xFFFFFFFF
+;mov dx,  #0x0cfc
+;out dx,  eax
 
 ;*****************************************************
 nop
@@ -166,14 +166,14 @@
 ;*****************************************************
 ; E) shadow - OFF (write)
 
-mov eax, #0x80000070
-mov dx,  #0x0cf8
-out dx,  eax
-
-;mov eax, #0xFFFFFFFF
-mov eax, #0x0000FFFF
-mov dx,  #0x0cfc
-out dx,  eax
+;mov eax, #0x80000070
+;mov dx,  #0x0cf8
+;out dx,  eax
+;
+;;mov eax, #0xFFFFFFFF
+;mov eax, #0x0000FFFF
+;mov dx,  #0x0cfc
+;out dx,  eax
 
 ;*****************************************************
 nop
@@ -262,14 +262,17 @@
 ; 077F - 10     = 07 6F 
 ; 07 6F - 00 F0 = 06 7F
 
+; for EPIA with 64MB RAM and 8MB frame buffer
+; 0370 - 00F0  = 02 80
+
 mov  al, #0x35 ;; cmos_reg
 out  0x70, al
-mov  al, #0x06 ;; val 
+mov  al, #0x02 ;; val 
 out  0x71, al
 
 mov  al, #0x34 ;; cmos_reg
 out  0x70, al
-mov  al, #0x7F ;; val 
+mov  al, #0x80 ;; val 
 out  0x71, al
 
 mov  al, #0x31 ;; cmos_reg
Binary files freebios-cvs/util/ADLO/payload and freebios-vga/util/ADLO/payload differ
Binary files freebios-cvs/util/ADLO/pirq/pirq-EPIA.bin and freebios-vga/util/ADLO/pirq/pirq-EPIA.bin differ
Binary files freebios-cvs/util/ADLO/video/video.bios-EPIA-64kb.bin and freebios-vga/util/ADLO/video/video.bios-EPIA-64kb.bin differ
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#
# LinuxBIOS config file for: VIA epia mini-itx
# with ADLO and manufacturer's VGA BIOS
#

target epia-vga

# via epia
mainboard via/epia

# Enable Serial Console for debugging
option SERIAL_CONSOLE=1
option TTYS0_BAUD=115200
option MAXIMUM_CONSOLE_LOGLEVEL=8
option DEFAULT_CONSOLE_LOGLEVEL=8
option DEBUG=1
option SERIAL_POST=1

# Use 256KB Standard Flash as Normal BIOS 
option RAMTEST=1
option STD_FLASH=1
option ZKERNEL_START=0xfffc0000
option ROM_SIZE=262144

# payload size
option PAYLOAD_SIZE=196608

# use ELF Loader
option USE_ELF_BOOT=1

# Boot payload in IDE disk partition
#option BOOT_IDE=1
#option CONFIG_UDELAY_TSC=1

# Boot payload in ROM
option USE_GENERIC_ROM=1

# our payload 
#payload /home/ts1/memtest86-3.0/memtest
payload /home/ts1/freebios-vga/util/ADLO/payload

# Enable video
option HAVE_FRAMEBUFFER=1


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