Flashing Bios Success...

Nathanael Noblet nathanael at gnat.ca
Thu May 8 12:54:00 CEST 2003


On Thursday, May 8, 2003, at 10:56  AM, Peter Stuge wrote:
>
> To clarify this a bit;
>
> Most flash ROM chips are identified, erased and programmed according 
> to a
> standard set by JEDEC.
>
> E.g. for byte-program:
>
> Write 0xaah to address 0x5555h in the ROM.
> Write 0x55h to address 0x2aaah in the ROM.
> Write 0xa0h to address 0x5555h in the ROM.
> Write byte-data to desired address in the ROM.
>
>
> Memory chips are identified by first entering the software-id mode:
> Write 0xaah to address 0x5555h in the ROM.
> Write 0x55h to address 0x2aaah in the ROM.
> Write 0x90h to address 0x5555h in the ROM.
>
> Now the 'manufacturer ID' and the 'device ID' bytes can be read from
> addresses 0 and 1 in the ROM, respectively.
>
> After reading the IDs, exit software-id mode thusly:
> Write 0xaah to address 0x5555h in the ROM.
> Write 0x55h to address 0x2aaah in the ROM.
> Write 0xf0h to address 0x5555h in the ROM.
>
> And so on. Grab a datasheet for the flash ROM chip you are working 
> with,
> this will most likely be documented there too.

I have these, the problem is in detecting the flash in the first place, 
these sequences of commands don't return what they should. Ron is 
telling me this is because the write enable bit isn't set. So I now 
have the docks for the SiS5595 that I didn't know I had (doesn't show 
in lspci). So what I need to know is how to get access to the registers 
in the SiS 5595 that set the write enable so that we can detect it 
properly... and then all the JEDEC stuff would work.

-- 
Nathanael Noblet
Gnat Solutions
4604 Monterey Ave NW
Calgary, AB
T3B 5K4

T/F 403.288.5360
C 403.809.5368

http://www.gnat.ca/




More information about the coreboot mailing list