proposed change to piix4e RFC

Ronald G. Minnich rminnich at
Thu Nov 14 21:54:01 CET 2002

I note the following code in src/mainboard/intel/l440gx/mainbard.c

        printk_debug("enabling smbus\n");
#if 0
        smbus_io = NewPciIo(0x10);
        smbus_io = 0xFFF0;
        pci_write_config_dword(pm_pcidev, 0x90, smbus_io | 1); /* iobase 
addr */
        pci_write_config_byte(pm_pcidev, 0xd2,  (0x4 << 1) | 1); /* smbus 
enable */
        pci_write_config_word(pm_pcidev, 0x4, 1); /* iospace enable */

        printk_debug("enable pm functions\n");
#if 0
        pm_io = NewPciIo(0x40);
        pm_io = 0xFF80;
        pci_write_config_dword(pm_pcidev, 0x40, pm_io | 1); /* iobase addr 
        pci_write_config_byte(pm_pcidev, 0x80, 1);  /* enable pm io 
address */

This code sets the base addresses of the piix4e smbus and PM to reasonable 
values < 0x1000. This would fix a problem I have had on the smartcore p5, 
where the PM and SMBUS were getting mapped to 0x1000 and 0x1040 in early 
assembly startup, and the PCI was starting I/O allocation at 0x1000, with 
the result that some I/O devices did not work correctly -- their I/O was 
preempted by the piix4e SMBUS and PM I/O. 

A question to this group: Doesn't it make more sense to put this code in 
the piix4e/southbridge.c file? The way it is now, some mainboards get 
fixed but others don't. Is there a problem with doing this?

Unless this causes trouble I would like to move this chunk of code so that 
all boards that use the piix4e can benefit from it.



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