[coreboot-gerrit] Change in coreboot[master]: cpu/intel/model_206ax: detect number of MCE banks

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/28443 )

Change subject: cpu/intel/model_206ax: detect number of MCE banks
......................................................................

cpu/intel/model_206ax: detect number of MCE banks

My CPU (3770k) supports 9 MCE banks, but the code is hardcoded to reset
only 7. This causes Linux to spuriously log errors during boot and S3
resume.

Fix this by reading the real value from the right MSR.

Change-Id: Id05645009259fd77b4de49bde518361eeae46617
Signed-off-by: Dan Elkouby <streetwalkermc at gmail.com>
Reviewed-on: https://review.coreboot.org/28443
Tested-by: build bot (Jenkins) <no-reply at coreboot.org>
Reviewed-by: Tristan Corrick <tristan at corrick.kiwi>
Reviewed-by: Elyes HAOUAS <ehaouas at noos.fr>
Reviewed-by: Patrick Rudolph <siro at das-labor.org>
---
M src/cpu/intel/model_206ax/model_206ax.h
M src/cpu/intel/model_206ax/model_206ax_init.c
2 files changed, 6 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Elyes HAOUAS: Looks good to me, but someone else must approve
  Patrick Rudolph: Looks good to me, approved
  Tristan Corrick: Looks good to me, but someone else must approve



diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h
index 7cb4069..98203b6 100644
--- a/src/cpu/intel/model_206ax/model_206ax.h
+++ b/src/cpu/intel/model_206ax/model_206ax.h
@@ -39,6 +39,7 @@
 #define IA32_PACKAGE_THERM_INTERRUPT	0x1b2
 #define MSR_LT_LOCK_MEMORY		0x2e7
 #define IA32_MC0_STATUS			0x401
+#define IA32_MCG_CAP			0x179
 
 #define MSR_PIC_MSG_CONTROL		0x2e
 #define MSR_PLATFORM_INFO		0xce
diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c
index 75631c1..3cc8d82 100644
--- a/src/cpu/intel/model_206ax/model_206ax_init.c
+++ b/src/cpu/intel/model_206ax/model_206ax_init.c
@@ -414,10 +414,14 @@
 {
 	msr_t msr;
 	int i;
+	int num_banks;
+
+	msr = rdmsr(IA32_MCG_CAP);
+	num_banks = msr.lo & 0xff;
 
 	msr.lo = msr.hi = 0;
 	/* This should only be done on a cold boot */
-	for (i = 0; i < 7; i++)
+	for (i = 0; i < num_banks; i++)
 		wrmsr(IA32_MC0_STATUS + (i * 4), msr);
 }
 

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: Id05645009259fd77b4de49bde518361eeae46617
Gerrit-Change-Number: 28443
Gerrit-PatchSet: 3
Gerrit-Owner: Dan Elkouby <streetwalkermc at gmail.com>
Gerrit-Reviewer: Angel Pons <th3fanbus at gmail.com>
Gerrit-Reviewer: Dan Elkouby <streetwalkermc at gmail.com>
Gerrit-Reviewer: Elyes HAOUAS <ehaouas at noos.fr>
Gerrit-Reviewer: Patrick Georgi <pgeorgi at google.com>
Gerrit-Reviewer: Patrick Rudolph <siro at das-labor.org>
Gerrit-Reviewer: Tristan Corrick <tristan at corrick.kiwi>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
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