[coreboot-gerrit] Change in coreboot[master]: siemens/mc_apl1: Make the DDR memory swizzle data configurable

[Werner Zeh (Code Review)]

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/28730 )

Change subject: siemens/mc_apl1: Make the DDR memory swizzle data configurable
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Patch Set 1: Code-Review+2

(1 comment)

https://review.coreboot.org/#/c/28730/1/src/mainboard/siemens/mc_apl1/romstage.c
File src/mainboard/siemens/mc_apl1/romstage.c:

https://review.coreboot.org/#/c/28730/1/src/mainboard/siemens/mc_apl1/romstage.c@80
PS1, Line 80: sz
You could just have used (size_t)DQ_BITS_PER_DQS here directly as you have to break the line anyway and now have space. It would increase readability IMO and you can get rid of the variable sz. But it is up to you.



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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: I4954d0a00d1d5fc28a8dda45a9fb27f98d5c3f1e
Gerrit-Change-Number: 28730
Gerrit-PatchSet: 1
Gerrit-Owner: Mario Scheithauer <mario.scheithauer at siemens.com>
Gerrit-Reviewer: Werner Zeh <werner.zeh at siemens.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-Comment-Date: Wed, 26 Sep 2018 05:45:18 +0000
Gerrit-HasComments: Yes
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