[coreboot-gerrit] Change in coreboot[master]: [for test]soc/intel/fsp_broadwell_de: Fix IA32_MC0_STATUS clear and I...
Elyes HAOUAS (Code Review)
gerrit at coreboot.org
Mon Sep 24 18:54:59 CEST 2018
Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28727
Change subject: [for test]soc/intel/fsp_broadwell_de: Fix IA32_MC0_STATUS clear and IA32_MC0_CTL init
......................................................................
[for test]soc/intel/fsp_broadwell_de: Fix IA32_MC0_STATUS clear and IA32_MC0_CTL init
Change-Id: I0c08844f3b9732195be65e8dc8a382df57c09bc1
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/soc/intel/fsp_broadwell_de/cpu.c
M src/soc/intel/fsp_broadwell_de/include/soc/msr.h
2 files changed, 10 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/28727/1
diff --git a/src/soc/intel/fsp_broadwell_de/cpu.c b/src/soc/intel/fsp_broadwell_de/cpu.c
index a50c839..c11ccd3 100644
--- a/src/soc/intel/fsp_broadwell_de/cpu.c
+++ b/src/soc/intel/fsp_broadwell_de/cpu.c
@@ -128,11 +128,10 @@
static void configure_mca(void)
{
msr_t msr;
- const unsigned int mcg_cap_msr = 0x179;
int i;
int num_banks;
- msr = rdmsr(mcg_cap_msr);
+ msr = rdmsr(IA32_MCG_CAP);
num_banks = msr.lo & 0xff;
/* TODO(adurbin): This should only be done on a cold boot. Also, some
@@ -140,14 +139,15 @@
every bank. */
msr.lo = msr.hi = 0;
for (i = 0; i < num_banks; i++) {
- wrmsr(MSR_IA32_MC0_STATUS + (i * 4) + 1, msr);
- wrmsr(MSR_IA32_MC0_STATUS + (i * 4) + 2, msr);
- wrmsr(MSR_IA32_MC0_STATUS + (i * 4) + 3, msr);
+ /* Clear the machine check status */
+ wrmsr(IA32_MC0_STATUS + (i * 4), msr);
}
msr.lo = msr.hi = 0xffffffff;
- for (i = 0; i < num_banks; i++)
- wrmsr(MSR_IA32_MC0_STATUS + (i * 4), msr);
+ for (i = 0; i < num_banks; i++) {
+ /* Initialize machine checks */
+ wrmsr(IA32_MC0_CTL + (i * 4), msr);
+ }
}
static void broadwell_de_core_init(struct device *cpu)
diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h
index 6b87061..ffa33da 100644
--- a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h
+++ b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h
@@ -21,9 +21,11 @@
#define MSR_IA32_PLATFORM_ID 0x17
#define MSR_CORE_THREAD_COUNT 0x35
#define MSR_PLATFORM_INFO 0xce
+#define IA32_MCG_CAP 0x179
#define IA32_PERF_CTL 0x199
#define MSR_TURBO_RATIO_LIMIT 0x1ad
-#define MSR_IA32_MC0_STATUS 0x400
+#define IA32_MC0_CTL 0x400
+#define IA32_MC0_STATUS 0x401
#define MSR_PKG_POWER_SKU_UNIT 0x606
#define MSR_PKG_POWER_LIMIT 0x610
#define MSR_CONFIG_TDP_NOMINAL 0x648
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I0c08844f3b9732195be65e8dc8a382df57c09bc1
Gerrit-Change-Number: 28727
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
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