[coreboot-gerrit] Change in coreboot[master]: mb/google/poppy/variants/nocturne: Stop charging with highest priority

[Sumeet R Pawnikar (Code Review)]

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/28723


Change subject: mb/google/poppy/variants/nocturne: Stop charging with highest priority
......................................................................

mb/google/poppy/variants/nocturne: Stop charging with highest priority

First stop battery charging at high temperature of TSR2 sensor and
later start CPU throttling for TSR2 sensor. This will control the
TSR2 sensor temperature going high and prevent to hit critical
temperature threshold for TSR2 to avoid shutdown.

BUG=b:112550414
BRANCH=None
TEST=Build coreboot for Nocturne board.

Change-Id: I22bf648ff31f7bdf0ce0d147399d4f566ccdddc3
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar at intel.com>
---
M src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl
1 file changed, 4 insertions(+), 3 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/28723/1

diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl
index f9773b8..6250cea 100644
--- a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl
+++ b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl
@@ -46,6 +46,7 @@
 	Package () { 0, 0, 0, 0, 24, 0x800, "mA", 0 },	/* 2000mA */
 	Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 },	/* 1000mA */
 	Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 },	/* 500mA */
+	Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 },	/* 0.0mA (stop charging) */
 })
 
 Name (DTRT, Package () {
@@ -56,17 +57,17 @@
 	Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
 
 	/* CPU Throttle Effect on DRAM (TSR2) */
-	Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
+	Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 50, 0, 0, 0, 0 },
 
 	/* CPU Throttle Effect on eMMC (TSR3) */
 	Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR3, 100, 600, 0, 0, 0, 0 },
 
 #ifdef DPTF_ENABLE_CHARGER
 	/* Charger Throttle Effect on Charger (TSR1) */
-	Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },
+	Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 50, 0, 0, 0, 0 },
 
 	/* Charger Throttle Effect on DRAM (TSR2) */
-	Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
+	Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 200, 50, 0, 0, 0, 0 },
 #endif
 })
 

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I22bf648ff31f7bdf0ce0d147399d4f566ccdddc3
Gerrit-Change-Number: 28723
Gerrit-PatchSet: 1
Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar at intel.com>
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