[coreboot-gerrit] Change in coreboot[master]: soc/amd/stoneyridge/romstage.c: Move STAPM code to SOC specific
Richard Spiegel (Code Review)
gerrit at coreboot.org
Thu Sep 20 23:50:30 CEST 2018
Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/28705
Change subject: soc/amd/stoneyridge/romstage.c: Move STAPM code to SOC specific
......................................................................
soc/amd/stoneyridge/romstage.c: Move STAPM code to SOC specific
STAPM programming was created inside function OemCustomizeInitEarly().
It should be SOC specific, and called by agesawarpper just before the
call to OemCustomizeInitEarly().
BUG=b:116196626
TEST=build and boot grunt
Change-Id: I8a2e51abda11a9d60a9057b38f2a484e1c8c9047
Signed-off-by: Richard Spiegel <richard.spiegel at silverbackltd.com>
---
M src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c
M src/soc/amd/common/block/include/amdblocks/agesawrapper.h
M src/soc/amd/common/block/pi/agesawrapper.c
M src/soc/amd/stoneyridge/romstage.c
4 files changed, 27 insertions(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/28705/1
diff --git a/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c b/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c
index 74578c2..cdc1fe0 100644
--- a/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c
+++ b/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c
@@ -149,27 +149,8 @@
/*---------------------------------------------------------------------------*/
VOID __weak OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly)
{
- const struct soc_amd_stoneyridge_config *cfg;
- const struct device *dev = dev_find_slot(0, GNB_DEVFN);
- struct _PLATFORM_CONFIGURATION *platform;
-
InitEarly->GnbConfig.PcieComplexList = (void *)&PcieComplex;
InitEarly->GnbConfig.PsppPolicy = PsppBalanceLow;
InitEarly->PlatformConfig.GnbAzI2sBusSelect = GnbAcpI2sBus;
InitEarly->PlatformConfig.GnbAzI2sBusPinConfig = GnbAcp2Tx4RxBluetooth;
- if (!dev || !dev->chip_info) {
- printk(BIOS_WARNING, "Warning: Cannot find SoC devicetree"
- " config, STAPM unchanged\n");
- return;
- }
- cfg = dev->chip_info;
- platform = &InitEarly->PlatformConfig;
- if ((cfg->stapm_percent) && (cfg->stapm_time) && (cfg->stapm_power)) {
- platform->PlatStapmConfig.CfgStapmScalar = cfg->stapm_percent;
- platform->PlatStapmConfig.CfgStapmTimeConstant =
- cfg->stapm_time;
- platform->PkgPwrLimitDC = cfg->stapm_power;
- platform->PkgPwrLimitAC = cfg->stapm_power;
- platform->PlatStapmConfig.CfgStapmBoost = StapmBoostEnabled;
- }
}
diff --git a/src/soc/amd/common/block/include/amdblocks/agesawrapper.h b/src/soc/amd/common/block/include/amdblocks/agesawrapper.h
index 9429366..713f76c 100644
--- a/src/soc/amd/common/block/include/amdblocks/agesawrapper.h
+++ b/src/soc/amd/common/block/include/amdblocks/agesawrapper.h
@@ -63,5 +63,6 @@
void SetFchMidParams(FCH_INTERFACE *params);
void SetNbMidParams(GNB_MID_CONFIGURATION *params);
void set_board_env_params(GNB_ENV_CONFIGURATION *params);
+void soc_customize_init_early(AMD_EARLY_PARAMS *InitEarly);
#endif /* __AGESAWRAPPER_H__ */
diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c
index 5cd04ba..7ef2bda 100644
--- a/src/soc/amd/common/block/pi/agesawrapper.c
+++ b/src/soc/amd/common/block/pi/agesawrapper.c
@@ -31,6 +31,8 @@
#include <amdblocks/image.h>
#include <amdblocks/BiosCallOuts.h>
#include <soc/southbridge.h>
+#include <soc/northbridge.h>
+#include <soc/cpu.h>
void __weak SetMemParams(AMD_POST_PARAMS *PostParams) {}
void __weak OemPostParams(AMD_POST_PARAMS *PostParams) {}
@@ -129,6 +131,7 @@
AMD_EARLY_PARAMS *EarlyParams = create_struct(&AmdParamStruct);
+ soc_customize_init_early(EarlyParams);
OemCustomizeInitEarly(EarlyParams);
timestamp_add_now(TS_AGESA_INIT_EARLY_START);
diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c
index de22191..a5acaf6 100644
--- a/src/soc/amd/stoneyridge/romstage.c
+++ b/src/soc/amd/stoneyridge/romstage.c
@@ -222,3 +222,26 @@
break;
}
}
+
+void soc_customize_init_early(AMD_EARLY_PARAMS *InitEarly)
+{
+ const struct soc_amd_stoneyridge_config *cfg;
+ const struct device *dev = dev_find_slot(0, GNB_DEVFN);
+ struct _PLATFORM_CONFIGURATION *platform;
+
+ if (!dev || !dev->chip_info) {
+ printk(BIOS_WARNING, "Warning: Cannot find SoC devicetree"
+ " config, STAPM unchanged\n");
+ return;
+ }
+ cfg = dev->chip_info;
+ platform = &InitEarly->PlatformConfig;
+ if ((cfg->stapm_percent) && (cfg->stapm_time) && (cfg->stapm_power)) {
+ platform->PlatStapmConfig.CfgStapmScalar = cfg->stapm_percent;
+ platform->PlatStapmConfig.CfgStapmTimeConstant =
+ cfg->stapm_time;
+ platform->PkgPwrLimitDC = cfg->stapm_power;
+ platform->PkgPwrLimitAC = cfg->stapm_power;
+ platform->PlatStapmConfig.CfgStapmBoost = StapmBoostEnabled;
+ }
+}
--
To view, visit https://review.coreboot.org/28705
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I8a2e51abda11a9d60a9057b38f2a484e1c8c9047
Gerrit-Change-Number: 28705
Gerrit-PatchSet: 1
Gerrit-Owner: Richard Spiegel <richard.spiegel at silverbackltd.com>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20180920/635c0efb/attachment-0001.html>
More information about the coreboot-gerrit
mailing list