[coreboot-gerrit] Change in coreboot[master]: src/drivers/intel/fsp1_1: Configure UART after memory init

[Frans Hendriks (Code Review)]

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/28464 )

Change subject: src/drivers/intel/fsp1_1: Configure UART after memory init
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Patch Set 1:

> Patch Set 1:
> 
> There should be an UPD to configure FSP to enable / disable the onboard UART. Am I wrong ?

Braswell FSP MR2 does not have UPD to enable/disable onboard UART.


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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: Ibb6c9e4153b3de58791b211c7f4241be3bceae9d
Gerrit-Change-Number: 28464
Gerrit-PatchSet: 1
Gerrit-Owner: Frans Hendriks <fhendriks at eltan.com>
Gerrit-Reviewer: Frans Hendriks <fhendriks at eltan.com>
Gerrit-Reviewer: Hannah Williams <hannah.williams at intel.com>
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Gerrit-CC: Patrick Rudolph <siro at das-labor.org>
Gerrit-Comment-Date: Mon, 17 Sep 2018 09:34:12 +0000
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