[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block: Don't use device_t in ramstage
Elyes HAOUAS (Code Review)
gerrit at coreboot.org
Sun Sep 16 17:37:01 CEST 2018
Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28631
Change subject: soc/intel/common/block: Don't use device_t in ramstage
......................................................................
soc/intel/common/block: Don't use device_t in ramstage
Use of device_t has been abandoned in ramstage.
Change-Id: If2d643eafea854563f56a7f867b7b492b6d09a19
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/soc/intel/common/block/include/intelblocks/acpi.h
M src/soc/intel/common/block/include/intelblocks/graphics.h
M src/soc/intel/common/block/include/intelblocks/mp_init.h
M src/soc/intel/common/block/lpc/lpc.c
M src/soc/intel/common/block/pcie/pcie.c
M src/soc/intel/common/block/smbus/smbus.c
M src/soc/intel/common/block/systemagent/systemagent.c
7 files changed, 15 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/28631/1
diff --git a/src/soc/intel/common/block/include/intelblocks/acpi.h b/src/soc/intel/common/block/include/intelblocks/acpi.h
index f58f914..6b1b9bd 100644
--- a/src/soc/intel/common/block/include/intelblocks/acpi.h
+++ b/src/soc/intel/common/block/include/intelblocks/acpi.h
@@ -42,7 +42,7 @@
* Calls acpi_write_hpet which creates and fills HPET table and
* adds it to the RSDT (and XSDT) structure.
*/
-unsigned long southbridge_write_acpi_tables(device_t device,
+unsigned long southbridge_write_acpi_tables(struct device *device,
unsigned long current,
struct acpi_rsdp *rsdp);
@@ -50,7 +50,7 @@
* Creates acpi gnvs and adds it to the DSDT table.
* GNVS creation is chipset specific and is done in soc specific acpi.c file.
*/
-void southbridge_inject_dsdt(device_t device);
+void southbridge_inject_dsdt(struct device *device);
/*
* This function populates the gnvs structure in acpi table.
diff --git a/src/soc/intel/common/block/include/intelblocks/graphics.h b/src/soc/intel/common/block/include/intelblocks/graphics.h
index f489e27..58f07ea 100644
--- a/src/soc/intel/common/block/include/intelblocks/graphics.h
+++ b/src/soc/intel/common/block/include/intelblocks/graphics.h
@@ -34,7 +34,7 @@
/*
* Write ASL entry for Graphics opregion
* Input:
- * device_t device: device structure
+ * strcut device *device: device structure
* current: start address of graphics opregion
* rsdp: pointer to RSDT (and XSDT) structure
*
diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h
index 4ad51d0..c5677e4 100644
--- a/src/soc/intel/common/block/include/intelblocks/mp_init.h
+++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h
@@ -75,7 +75,7 @@
* In this function SOC must perform CPU feature programming
* during Ramstage phase.
*/
-void soc_core_init(device_t dev);
+void soc_core_init(struct device *dev);
/*
* In this function SOC must fill required mp_ops params, also it
diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c
index c462d9d..ef8417a 100644
--- a/src/soc/intel/common/block/lpc/lpc.c
+++ b/src/soc/intel/common/block/lpc/lpc.c
@@ -46,7 +46,7 @@
res->flags = flags;
}
-static void pch_lpc_add_io_resources(device_t dev)
+static void pch_lpc_add_io_resources(struct device *dev)
{
/* Add the default claimed legacy IO range for the LPC device. */
pch_lpc_add_new_resource(dev, 0, 0, 0x1000, IORESOURCE_IO |
@@ -56,7 +56,7 @@
pch_lpc_soc_fill_io_resources(dev);
}
-static void pch_lpc_read_resources(device_t dev)
+static void pch_lpc_read_resources(struct device *dev)
{
/* Get the PCI resources of this device. */
pci_dev_read_resources(dev);
@@ -101,7 +101,7 @@
}
}
-static void pch_lpc_set_resources(device_t dev)
+static void pch_lpc_set_resources(struct device *dev)
{
pci_dev_set_resources(dev);
diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c
index 4cd057d..c4b266a 100644
--- a/src/soc/intel/common/block/pcie/pcie.c
+++ b/src/soc/intel/common/block/pcie/pcie.c
@@ -64,7 +64,7 @@
pci_write_config16(dev, PCI_SEC_STATUS, reg16);
}
-static void pcie_set_L1_ss_max_latency(device_t dev, unsigned int offset)
+static void pcie_set_L1_ss_max_latency(struct device *dev, unsigned int offset)
{
/* Set max snoop and non-snoop latency for the SOC */
pci_write_config32(dev, offset,
diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c
index 3793025..9bb9436 100644
--- a/src/soc/intel/common/block/smbus/smbus.c
+++ b/src/soc/intel/common/block/smbus/smbus.c
@@ -22,7 +22,7 @@
#include <soc/smbus.h>
#include "smbuslib.h"
-static int lsmbus_read_byte(device_t dev, u8 address)
+static int lsmbus_read_byte(struct device *dev, u8 address)
{
u16 device;
struct resource *res;
@@ -33,7 +33,7 @@
return smbus_read8(res->base, device, address);
}
-static int lsmbus_write_byte(device_t dev, u8 address, u8 data)
+static int lsmbus_write_byte(struct device *dev, u8 address, u8 data)
{
u16 device;
struct resource *res;
@@ -50,7 +50,7 @@
.write_byte = lsmbus_write_byte,
};
-static void pch_smbus_init(device_t dev)
+static void pch_smbus_init(struct device *dev)
{
struct resource *res;
@@ -64,7 +64,7 @@
outb(SMBUS_SLAVE_ADDR, res->base + SMB_RCV_SLVA);
}
-static void smbus_read_resources(device_t dev)
+static void smbus_read_resources(struct device *dev)
{
struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4);
res->base = SMBUS_IO_BASE;
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c
index 72cecb1..45ee940 100644
--- a/src/soc/intel/common/block/systemagent/systemagent.c
+++ b/src/soc/intel/common/block/systemagent/systemagent.c
@@ -88,7 +88,7 @@
};
/* Read DRAM memory map register value through PCI configuration space */
-static void sa_read_map_entry(device_t dev,
+static void sa_read_map_entry(struct device *dev,
const struct sa_mem_map_descriptor *entry, uint64_t *result)
{
uint64_t value = 0;
@@ -213,7 +213,8 @@
return !!(imr_base_reg & (1 << 31));
}
-static void imr_resource(device_t dev, int idx, uint32_t base, uint32_t mask)
+static void imr_resource(struct device *dev, int idx, uint32_t base,
+ uint32_t mask)
{
uint32_t base_k, size_k;
/* Bits 28:0 encode the base address bits 38:10, hence the KiB unit. */
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: If2d643eafea854563f56a7f867b7b492b6d09a19
Gerrit-Change-Number: 28631
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
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