[coreboot-gerrit] Change in coreboot[master]: [WIP] arch/riscv: Advance the instruction pointer after handling misa...

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28617 )

Change subject: [WIP] arch/riscv: Advance the instruction pointer after handling misaligned load/store
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Patch Set 1:

(1 comment)

https://review.coreboot.org/#/c/28617/1/src/arch/riscv/misaligned.c
File src/arch/riscv/misaligned.c:

https://review.coreboot.org/#/c/28617/1/src/arch/riscv/misaligned.c@273
PS1, Line 273: 	write_csr(mepc, read_csr(mepc) + is_compressed? 2:4);
spaces required around that '?' (ctx:VxW)



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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: Ie2dc0083835809971143cd6ab89fe4f7acd2a845
Gerrit-Change-Number: 28617
Gerrit-PatchSet: 1
Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
Gerrit-CC: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-Comment-Date: Sat, 15 Sep 2018 11:52:33 +0000
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