[coreboot-gerrit] Change in coreboot[rampayload]: WIP: Port libpayload to riscv

build bot (Jenkins) (Code Review) gerrit at coreboot.org
Sat Sep 15 10:42:07 CEST 2018


build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28606 )

Change subject: WIP: Port libpayload to riscv
......................................................................


Patch Set 3:

(38 comments)

https://review.coreboot.org/#/c/28606/3/payloads/external/LinuxBoot/Makefile
File payloads/external/LinuxBoot/Makefile:

https://review.coreboot.org/#/c/28606/3/payloads/external/LinuxBoot/Makefile@78
PS3, Line 78: 	echo "BEFOR DEF"
'BEFOR' may be misspelled - perhaps 'BEFORE'?


https://review.coreboot.org/#/c/28606/3/payloads/libpayload/arch/riscv/coreboot.c
File payloads/libpayload/arch/riscv/coreboot.c:

https://review.coreboot.org/#/c/28606/3/payloads/libpayload/arch/riscv/coreboot.c@42
PS3, Line 42: 	switch(rec->tag) {
space required before the open parenthesis '('


https://review.coreboot.org/#/c/28606/3/payloads/libpayload/include/riscv/arch/asm.h
File payloads/libpayload/include/riscv/arch/asm.h:

https://review.coreboot.org/#/c/28606/3/payloads/libpayload/include/riscv/arch/asm.h@14
PS3, Line 14: #define ALIGN .align 2
Macros with complex values should be enclosed in parentheses


https://review.coreboot.org/#/c/28606/3/payloads/libpayload/include/riscv/arch/asm.h@16
PS3, Line 16: #define ENDPROC(name) \
Macros with multiple statements should be enclosed in a do - while loop


https://review.coreboot.org/#/c/28606/3/payloads/libpayload/include/riscv/arch/asm.h@17
PS3, Line 17: 	.type name, %function; \
need consistent spacing around '%' (ctx:WxV)


https://review.coreboot.org/#/c/28606/3/payloads/libpayload/include/riscv/arch/asm.h@20
PS3, Line 20: #define ENTRY(name) \
Macros with multiple statements should be enclosed in a do - while loop


https://review.coreboot.org/#/c/28606/3/payloads/libpayload/include/riscv/arch/asm.h@21
PS3, Line 21: 	.section .text.name, "ax", %progbits; \
need consistent spacing around '%' (ctx:WxV)


https://review.coreboot.org/#/c/28606/3/payloads/libpayload/include/riscv/arch/asm.h@24
PS3, Line 24: 	name:
labels should not be indented


https://review.coreboot.org/#/c/28606/3/payloads/libpayload/include/riscv/arch/asm.h@26
PS3, Line 26: #define END(name) \
Macros with complex values should be enclosed in parentheses


https://review.coreboot.org/#/c/28606/3/payloads/libpayload/include/riscv/arch/asm.h@27
PS3, Line 27: 	.size name, .-name
space required before that '-' (ctx:VxV)


https://review.coreboot.org/#/c/28606/3/payloads/libpayload/include/riscv/arch/barrier.h
File payloads/libpayload/include/riscv/arch/barrier.h:

https://review.coreboot.org/#/c/28606/3/payloads/libpayload/include/riscv/arch/barrier.h@57
PS3, Line 57: #define mb()
memory barrier without comment


https://review.coreboot.org/#/c/28606/3/payloads/libpayload/include/riscv/arch/barrier.h@58
PS3, Line 58: #define rmb()
memory barrier without comment


https://review.coreboot.org/#/c/28606/3/payloads/libpayload/include/riscv/arch/barrier.h@59
PS3, Line 59: #define wmb()
memory barrier without comment


https://review.coreboot.org/#/c/28606/3/payloads/libpayload/include/riscv/arch/cache.h
File payloads/libpayload/include/riscv/arch/cache.h:

https://review.coreboot.org/#/c/28606/3/payloads/libpayload/include/riscv/arch/cache.h@81
PS3, Line 81: }
void function return statements are not generally useful


https://review.coreboot.org/#/c/28606/3/payloads/linuxcheck/riscv-fu540.c
File payloads/linuxcheck/riscv-fu540.c:

https://review.coreboot.org/#/c/28606/3/payloads/linuxcheck/riscv-fu540.c@25
PS3, Line 25:         uint32_t txdata;        /* Transmit data register */
code indent should use tabs where possible


https://review.coreboot.org/#/c/28606/3/payloads/linuxcheck/riscv-fu540.c@25
PS3, Line 25:         uint32_t txdata;        /* Transmit data register */
please, no spaces at the start of a line


https://review.coreboot.org/#/c/28606/3/payloads/linuxcheck/riscv-fu540.c@26
PS3, Line 26:         uint32_t rxdata;        /* Receive data register */
code indent should use tabs where possible


https://review.coreboot.org/#/c/28606/3/payloads/linuxcheck/riscv-fu540.c@26
PS3, Line 26:         uint32_t rxdata;        /* Receive data register */
please, no spaces at the start of a line


https://review.coreboot.org/#/c/28606/3/payloads/linuxcheck/riscv-fu540.c@27
PS3, Line 27:         uint32_t txctrl;        /* Transmit control register */
code indent should use tabs where possible


https://review.coreboot.org/#/c/28606/3/payloads/linuxcheck/riscv-fu540.c@27
PS3, Line 27:         uint32_t txctrl;        /* Transmit control register */
please, no spaces at the start of a line


https://review.coreboot.org/#/c/28606/3/payloads/linuxcheck/riscv-fu540.c@28
PS3, Line 28:         uint32_t rxctrl;        /* Receive control register */
code indent should use tabs where possible


https://review.coreboot.org/#/c/28606/3/payloads/linuxcheck/riscv-fu540.c@28
PS3, Line 28:         uint32_t rxctrl;        /* Receive control register */
please, no spaces at the start of a line


https://review.coreboot.org/#/c/28606/3/payloads/linuxcheck/riscv-fu540.c@29
PS3, Line 29:         uint32_t ie;            /* UART interrupt enable */
code indent should use tabs where possible


https://review.coreboot.org/#/c/28606/3/payloads/linuxcheck/riscv-fu540.c@29
PS3, Line 29:         uint32_t ie;            /* UART interrupt enable */
please, no spaces at the start of a line


https://review.coreboot.org/#/c/28606/3/payloads/linuxcheck/riscv-fu540.c@30
PS3, Line 30:         uint32_t ip;            /* UART interrupt pending */
code indent should use tabs where possible


https://review.coreboot.org/#/c/28606/3/payloads/linuxcheck/riscv-fu540.c@30
PS3, Line 30:         uint32_t ip;            /* UART interrupt pending */
please, no spaces at the start of a line


https://review.coreboot.org/#/c/28606/3/payloads/linuxcheck/riscv-fu540.c@31
PS3, Line 31:         uint32_t div;           /* Baud rate divisor */
code indent should use tabs where possible


https://review.coreboot.org/#/c/28606/3/payloads/linuxcheck/riscv-fu540.c@31
PS3, Line 31:         uint32_t div;           /* Baud rate divisor */
please, no spaces at the start of a line


https://review.coreboot.org/#/c/28606/3/payloads/linuxcheck/riscv-fu540.c@36
PS3, Line 36:         return !(read32(&regs->txdata) & TXDATA_FULL);
code indent should use tabs where possible


https://review.coreboot.org/#/c/28606/3/payloads/linuxcheck/riscv-fu540.c@36
PS3, Line 36:         return !(read32(&regs->txdata) & TXDATA_FULL);
please, no spaces at the start of a line


https://review.coreboot.org/#/c/28606/3/payloads/linuxcheck/riscv-fu540.c@41
PS3, Line 41:         struct sifive_uart_registers *regs = (void *)(FU540_UART(idx));
code indent should use tabs where possible


https://review.coreboot.org/#/c/28606/3/payloads/linuxcheck/riscv-fu540.c@41
PS3, Line 41:         struct sifive_uart_registers *regs = (void *)(FU540_UART(idx));
please, no spaces at the start of a line


https://review.coreboot.org/#/c/28606/3/payloads/linuxcheck/riscv-fu540.c@43
PS3, Line 43:         while (!uart_can_tx(regs))
code indent should use tabs where possible


https://review.coreboot.org/#/c/28606/3/payloads/linuxcheck/riscv-fu540.c@43
PS3, Line 43:         while (!uart_can_tx(regs))
please, no spaces at the start of a line


https://review.coreboot.org/#/c/28606/3/payloads/linuxcheck/riscv-fu540.c@44
PS3, Line 44:                 ; /* TODO: implement a timeout */
code indent should use tabs where possible


https://review.coreboot.org/#/c/28606/3/payloads/linuxcheck/riscv-fu540.c@44
PS3, Line 44:                 ; /* TODO: implement a timeout */
please, no spaces at the start of a line


https://review.coreboot.org/#/c/28606/3/payloads/linuxcheck/riscv-fu540.c@46
PS3, Line 46:         write32(&regs->txdata, data);
code indent should use tabs where possible


https://review.coreboot.org/#/c/28606/3/payloads/linuxcheck/riscv-fu540.c@46
PS3, Line 46:         write32(&regs->txdata, data);
please, no spaces at the start of a line



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Gerrit-Project: coreboot
Gerrit-Branch: rampayload
Gerrit-MessageType: comment
Gerrit-Change-Id: I91df02069a0f8fd8771f73de0e866e9cea05cded
Gerrit-Change-Number: 28606
Gerrit-PatchSet: 3
Gerrit-Owner: Philipp Hug <philipp at hug.cx>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-Comment-Date: Sat, 15 Sep 2018 08:42:07 +0000
Gerrit-HasComments: Yes
Gerrit-HasLabels: No
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