[coreboot-gerrit] Change in coreboot[master]: soc/sifive/fu540: Initialize SDRAM

Fri Sep 14 11:54:42 CEST 2018

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28604 )

Change subject: soc/sifive/fu540: Initialize SDRAM
......................................................................

Patch Set 1:

(161 comments)

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h
File src/soc/sifive/fu540/ux00ddr.h:

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@39
PS1, Line 39: static inline void phy_reset(volatile uint32_t *ddrphyreg, const uint32_t *physettings) {
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@39
PS1, Line 39: static inline void phy_reset(volatile uint32_t *ddrphyreg, const uint32_t *physettings) {
open brace '{' following function definitions go on the next line

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@40
PS1, Line 40:   unsigned int i;
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@41
PS1, Line 41:   for (i=1152;i<=1214;i++) {
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@41
PS1, Line 41:   for (i=1152;i<=1214;i++) {
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@41
PS1, Line 41:   for (i=1152;i<=1214;i++) {
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@41
PS1, Line 41:   for (i=1152;i<=1214;i++) {
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@41
PS1, Line 41:   for (i=1152;i<=1214;i++) {
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@41
PS1, Line 41:   for (i=1152;i<=1214;i++) {
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@42
PS1, Line 42:     uint32_t physet = physettings[i];
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@44
PS1, Line 44:   }
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@45
PS1, Line 45:   for (i=0;i<=1151;i++) {
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@45
PS1, Line 45:   for (i=0;i<=1151;i++) {
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@45
PS1, Line 45:   for (i=0;i<=1151;i++) {
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@45
PS1, Line 45:   for (i=0;i<=1151;i++) {
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@45
PS1, Line 45:   for (i=0;i<=1151;i++) {
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@45
PS1, Line 45:   for (i=0;i<=1151;i++) {
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@46
PS1, Line 46:     uint32_t physet = physettings[i];
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@48
PS1, Line 48:   }
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@52
PS1, Line 52: static inline void ux00ddr_writeregmap(size_t ahbregaddr, const uint32_t *ctlsettings, const uint32_t *physettings) {
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@52
PS1, Line 52: static inline void ux00ddr_writeregmap(size_t ahbregaddr, const uint32_t *ctlsettings, const uint32_t *physettings) {
open brace '{' following function definitions go on the next line

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@53
PS1, Line 53:   volatile uint32_t *ddrctlreg = (volatile uint32_t *) ahbregaddr;
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@54
PS1, Line 54:   volatile uint32_t *ddrphyreg = ((volatile uint32_t *) ahbregaddr) + (0x2000 / sizeof(uint32_t));
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@54
PS1, Line 54:   volatile uint32_t *ddrphyreg = ((volatile uint32_t *) ahbregaddr) + (0x2000 / sizeof(uint32_t));
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@56
PS1, Line 56:   unsigned int i;
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@57
PS1, Line 57:   for (i=0;i<=264;i++) {
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@57
PS1, Line 57:   for (i=0;i<=264;i++) {
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@57
PS1, Line 57:   for (i=0;i<=264;i++) {
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@57
PS1, Line 57:   for (i=0;i<=264;i++) {
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@57
PS1, Line 57:   for (i=0;i<=264;i++) {
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@57
PS1, Line 57:   for (i=0;i<=264;i++) {
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@58
PS1, Line 58:     uint32_t ctlset = ctlsettings[i];
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@60
PS1, Line 60:   }
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@62
PS1, Line 62:   phy_reset(ddrphyreg, physettings);
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@65
PS1, Line 65: static inline void ux00ddr_start(size_t ahbregaddr, size_t filteraddr, size_t ddrend) {
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@65
PS1, Line 65: static inline void ux00ddr_start(size_t ahbregaddr, size_t filteraddr, size_t ddrend) {
open brace '{' following function definitions go on the next line

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@67
PS1, Line 67:   uint32_t regdata = _REG32(0<<2, ahbregaddr);
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@68
PS1, Line 68:   regdata |= 0x1;
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@69
PS1, Line 69:   _REG32(0<<2, ahbregaddr) = regdata;
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@70
PS1, Line 70:   // WAIT for initialization complete : bit 8 of INT_STATUS (DENALI_CTL_132) 0x210
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@71
PS1, Line 71:   while ((_REG32(132<<2, ahbregaddr) & (1<<MC_INIT_COMPLETE_OFFSET)) == 0) {}
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@71
PS1, Line 71:   while ((_REG32(132<<2, ahbregaddr) & (1<<MC_INIT_COMPLETE_OFFSET)) == 0) {}
trailing statements should be on next line

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@71
PS1, Line 71:   while ((_REG32(132<<2, ahbregaddr) & (1<<MC_INIT_COMPLETE_OFFSET)) == 0) {}
braces {} are not necessary for single statement blocks

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@74
PS1, Line 74:   volatile uint64_t *filterreg = (volatile uint64_t *)filteraddr;
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@75
PS1, Line 75:   filterreg[0] = 0x0f00000000000000UL | (ddrend >> 2);
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@79
PS1, Line 79: static inline void ux00ddr_mask_mc_init_complete_interrupt(size_t ahbregaddr) {
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@82
PS1, Line 82:   _REG32(136<<2, ahbregaddr) |= (1<<MC_INIT_COMPLETE_OFFSET);
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@85
PS1, Line 85: static inline void ux00ddr_mask_outofrange_interrupts(size_t ahbregaddr) {
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@87
PS1, Line 87:   // Bit [2] Multiple accesses outside the defined PHYSICAL memory space have occured
'occured' may be misspelled - perhaps 'occurred'?

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@87
PS1, Line 87:   // Bit [2] Multiple accesses outside the defined PHYSICAL memory space have occured
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@88
PS1, Line 88:   // Bit [1] A memory access outside the defined PHYSICAL memory space has occured
'occured' may be misspelled - perhaps 'occurred'?

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@88
PS1, Line 88:   // Bit [1] A memory access outside the defined PHYSICAL memory space has occured
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@89
PS1, Line 89:   _REG32(136<<2, ahbregaddr) |= ((1<<OUT_OF_RANGE_OFFSET) | (1<<MULTIPLE_OUT_OF_RANGE_OFFSET));
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@89
PS1, Line 89:   _REG32(136<<2, ahbregaddr) |= ((1<<OUT_OF_RANGE_OFFSET) | (1<<MULTIPLE_OUT_OF_RANGE_OFFSET));
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@92
PS1, Line 92: static inline void ux00ddr_mask_port_command_error_interrupt(size_t ahbregaddr) {
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@92
PS1, Line 92: static inline void ux00ddr_mask_port_command_error_interrupt(size_t ahbregaddr) {
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@94
PS1, Line 94:   // Bit [7] An error occured on the port command channel
'occured' may be misspelled - perhaps 'occurred'?

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@95
PS1, Line 95:   _REG32(136<<2, ahbregaddr) |= (1<<PORT_COMMAND_CHANNEL_ERROR_OFFSET);
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@98
PS1, Line 98: static inline void ux00ddr_mask_leveling_completed_interrupt(size_t ahbregaddr) {
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@98
PS1, Line 98: static inline void ux00ddr_mask_leveling_completed_interrupt(size_t ahbregaddr) {
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@101
PS1, Line 101:   _REG32(136<<2, ahbregaddr) |= (1<<LEVELING_OPERATION_COMPLETED_OFFSET);
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@104
PS1, Line 104: static inline void ux00ddr_setuprangeprotection(size_t ahbregaddr, size_t end_addr) {
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@104
PS1, Line 104: static inline void ux00ddr_setuprangeprotection(size_t ahbregaddr, size_t end_addr) {
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@105
PS1, Line 105:   _REG32(209<<2, ahbregaddr) = 0x0;
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@106
PS1, Line 106:   size_t end_addr_16Kblocks = ((end_addr >> 14) & 0x7FFFFF)-1;
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@107
PS1, Line 107:   _REG32(210<<2, ahbregaddr) = ((uint32_t) end_addr_16Kblocks);
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@108
PS1, Line 108:   _REG32(212<<2, ahbregaddr) = 0x0;
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@109
PS1, Line 109:   _REG32(214<<2, ahbregaddr) = 0x0;
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@110
PS1, Line 110:   _REG32(216<<2, ahbregaddr) = 0x0;
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@111
PS1, Line 111:   _REG32(224<<2, ahbregaddr) |= (0x3 << AXI0_RANGE_PROT_BITS_0_OFFSET);
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@112
PS1, Line 112:   _REG32(225<<2, ahbregaddr) = 0xFFFFFFFF;
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@113
PS1, Line 113:   _REG32(208<<2, ahbregaddr) |= (1 << AXI0_ADDRESS_RANGE_ENABLE);
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@114
PS1, Line 114:   _REG32(208<<2, ahbregaddr) |= (1 << PORT_ADDR_PROTECTION_EN_OFFSET);
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@118
PS1, Line 118: static inline void ux00ddr_disableaxireadinterleave(size_t ahbregaddr) {
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@119
PS1, Line 119:   _REG32(120<<2, ahbregaddr) |= (1<<DISABLE_RD_INTERLEAVE_OFFSET);
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@122
PS1, Line 122: static inline void ux00ddr_disableoptimalrmodw(size_t ahbregaddr) {
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@123
PS1, Line 123:   _REG32(21<<2, ahbregaddr) &= (~(1<<OPTIMAL_RMODW_EN_OFFSET));
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@126
PS1, Line 126: static inline void ux00ddr_enablewriteleveling(size_t ahbregaddr) {
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@127
PS1, Line 127:   _REG32(170<<2, ahbregaddr) |= ((1<<WRLVL_EN_OFFSET) | (1<<DFI_PHY_WRLELV_MODE_OFFSET));
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@127
PS1, Line 127:   _REG32(170<<2, ahbregaddr) |= ((1<<WRLVL_EN_OFFSET) | (1<<DFI_PHY_WRLELV_MODE_OFFSET));
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@130
PS1, Line 130: static inline void ux00ddr_enablereadleveling(size_t ahbregaddr) {
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@131
PS1, Line 131:   _REG32(181<<2, ahbregaddr) |= (1<<DFI_PHY_RDLVL_MODE_OFFSET);
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@132
PS1, Line 132:   _REG32(260<<2, ahbregaddr) |= (1<<RDLVL_EN_OFFSET);
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@135
PS1, Line 135: static inline void ux00ddr_enablereadlevelinggate(size_t ahbregaddr) {
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@136
PS1, Line 136:   _REG32(260<<2, ahbregaddr) |= (1<<RDLVL_GATE_EN_OFFSET);
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@137
PS1, Line 137:   _REG32(182<<2, ahbregaddr) |= (1<<DFI_PHY_RDLVL_GATE_MODE_OFFSET);
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@140
PS1, Line 140: static inline void ux00ddr_enablevreftraining(size_t ahbregaddr) {
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@141
PS1, Line 141:   _REG32(184<<2, ahbregaddr) |= (1<<VREF_EN_OFFSET);
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@144
PS1, Line 144: static inline uint32_t ux00ddr_getdramclass(size_t ahbregaddr) {
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@145
PS1, Line 145:   return ((_REG32(0, ahbregaddr) >> DRAM_CLASS_OFFSET) & 0xF);
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@148
PS1, Line 148: static inline uint64_t ux00ddr_phy_fixup(size_t ahbregaddr) {
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@151
PS1, Line 151:   size_t ddrphyreg = ahbregaddr + 0x2000;
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@153
PS1, Line 153:   uint64_t fails=0;
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@153
PS1, Line 153:   uint64_t fails=0;
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@154
PS1, Line 154:   uint32_t slicebase = 0;
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@155
PS1, Line 155:   uint32_t dq = 0;
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@158
PS1, Line 158:   for (uint32_t slice = 0; slice < 8; slice++) {
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https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@158
PS1, Line 158:   for (uint32_t slice = 0; slice < 8; slice++) {
suspect code indent for conditional statements (2, 4)

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@159
PS1, Line 159:     uint32_t regbase = slicebase + 34;
please, no spaces at the start of a line

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@160
PS1, Line 160:     for (uint32_t reg = 0 ; reg < 4; reg++) {
please, no spaces at the start of a line

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@160
PS1, Line 160:     for (uint32_t reg = 0 ; reg < 4; reg++) {
suspect code indent for conditional statements (4, 6)

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@161
PS1, Line 161:       uint32_t updownreg = _REG32((regbase+reg)<<2, ddrphyreg);
please, no spaces at the start of a line

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@162
PS1, Line 162:       for (uint32_t bit = 0; bit < 2; bit++) {
please, no spaces at the start of a line

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@163
PS1, Line 163:         uint32_t phy_rx_cal_dqn_0_offset;
code indent should use tabs where possible

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@163
PS1, Line 163:         uint32_t phy_rx_cal_dqn_0_offset;
please, no spaces at the start of a line

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@165
PS1, Line 165:         if (bit==0) {
code indent should use tabs where possible

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@165
PS1, Line 165:         if (bit==0) {
please, no spaces at the start of a line

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@165
PS1, Line 165:         if (bit==0) {
suspect code indent for conditional statements (8, 10)

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@165
PS1, Line 165:         if (bit==0) {
spaces required around that '==' (ctx:VxV)

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@165
PS1, Line 165:         if (bit==0) {
braces {} are not necessary for any arm of this statement

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@166
PS1, Line 166:           phy_rx_cal_dqn_0_offset = PHY_RX_CAL_DQ0_0_OFFSET;
code indent should use tabs where possible

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@166
PS1, Line 166:           phy_rx_cal_dqn_0_offset = PHY_RX_CAL_DQ0_0_OFFSET;
please, no spaces at the start of a line

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@167
PS1, Line 167:         }else{
code indent should use tabs where possible

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@167
PS1, Line 167:         }else{
please, no spaces at the start of a line

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@167
PS1, Line 167:         }else{
suspect code indent for conditional statements (8, 10)

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@167
PS1, Line 167:         }else{
space required after that close brace '}'

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@168
PS1, Line 168:           phy_rx_cal_dqn_0_offset = PHY_RX_CAL_DQ1_0_OFFSET;
code indent should use tabs where possible

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@168
PS1, Line 168:           phy_rx_cal_dqn_0_offset = PHY_RX_CAL_DQ1_0_OFFSET;
please, no spaces at the start of a line

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@169
PS1, Line 169:         }
code indent should use tabs where possible

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@169
PS1, Line 169:         }
please, no spaces at the start of a line

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@171
PS1, Line 171:         uint32_t down = (updownreg >> phy_rx_cal_dqn_0_offset) & 0x3F;
code indent should use tabs where possible

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@171
PS1, Line 171:         uint32_t down = (updownreg >> phy_rx_cal_dqn_0_offset) & 0x3F;
please, no spaces at the start of a line

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@172
PS1, Line 172:         uint32_t up = (updownreg >> (phy_rx_cal_dqn_0_offset+6)) & 0x3F;
code indent should use tabs where possible

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@172
PS1, Line 172:         uint32_t up = (updownreg >> (phy_rx_cal_dqn_0_offset+6)) & 0x3F;
please, no spaces at the start of a line

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@174
PS1, Line 174:         uint8_t failc0 = ((down == 0) && (up == 0x3F));
code indent should use tabs where possible

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@174
PS1, Line 174:         uint8_t failc0 = ((down == 0) && (up == 0x3F));
please, no spaces at the start of a line

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@175
PS1, Line 175:         uint8_t failc1 = ((up == 0) && (down == 0x3F));
code indent should use tabs where possible

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@175
PS1, Line 175:         uint8_t failc1 = ((up == 0) && (down == 0x3F));
please, no spaces at the start of a line

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@177
PS1, Line 177:         // print error message on failure
code indent should use tabs where possible

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@178
PS1, Line 178:         if (failc0 || failc1) {
code indent should use tabs where possible

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@178
PS1, Line 178:         if (failc0 || failc1) {
please, no spaces at the start of a line

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@178
PS1, Line 178:         if (failc0 || failc1) {
suspect code indent for conditional statements (8, 10)

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@179
PS1, Line 179:           //if (fails==0) uart_puts((void*) UART0_CTRL_ADDR, "DDR error in fixing up \n");
line over 80 characters

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@179
PS1, Line 179:           //if (fails==0) uart_puts((void*) UART0_CTRL_ADDR, "DDR error in fixing up \n");
code indent should use tabs where possible

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@179
PS1, Line 179:           //if (fails==0) uart_puts((void*) UART0_CTRL_ADDR, "DDR error in fixing up \n");
unnecessary whitespace before a quoted newline

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@180
PS1, Line 180:           fails |= (1<<dq);
code indent should use tabs where possible

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@180
PS1, Line 180:           fails |= (1<<dq);
please, no spaces at the start of a line

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@181
PS1, Line 181:           char slicelsc = '0';
code indent should use tabs where possible

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@181
PS1, Line 181:           char slicelsc = '0';
please, no spaces at the start of a line

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@182
PS1, Line 182:           char slicemsc = '0';
code indent should use tabs where possible

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@182
PS1, Line 182:           char slicemsc = '0';
please, no spaces at the start of a line

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@183
PS1, Line 183:           slicelsc += (dq % 10);
code indent should use tabs where possible

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@183
PS1, Line 183:           slicelsc += (dq % 10);
please, no spaces at the start of a line

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@184
PS1, Line 184:           slicemsc += (dq / 10);
code indent should use tabs where possible

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@184
PS1, Line 184:           slicemsc += (dq / 10);
please, no spaces at the start of a line

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@185
PS1, Line 185:           //uart_puts((void*) UART0_CTRL_ADDR, "S ");
code indent should use tabs where possible

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@186
PS1, Line 186:           //uart_puts((void*) UART0_CTRL_ADDR, &slicemsc);
code indent should use tabs where possible

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@187
PS1, Line 187:           //uart_puts((void*) UART0_CTRL_ADDR, &slicelsc);
code indent should use tabs where possible

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@188
PS1, Line 188:           //if (failc0) uart_puts((void*) UART0_CTRL_ADDR, "U");
code indent should use tabs where possible

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@189
PS1, Line 189:           //else uart_puts((void*) UART0_CTRL_ADDR, "D");
code indent should use tabs where possible

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@190
PS1, Line 190:           //uart_puts((void*) UART0_CTRL_ADDR, "\n");
code indent should use tabs where possible

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@191
PS1, Line 191:         }
code indent should use tabs where possible

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@191
PS1, Line 191:         }
please, no spaces at the start of a line

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@192
PS1, Line 192:         dq++;
code indent should use tabs where possible

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@192
PS1, Line 192:         dq++;
please, no spaces at the start of a line

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@193
PS1, Line 193:       }
please, no spaces at the start of a line

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@194
PS1, Line 194:     }
please, no spaces at the start of a line

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@195
PS1, Line 195:     slicebase+=128;
please, no spaces at the start of a line

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@195
PS1, Line 195:     slicebase+=128;
spaces required around that '+=' (ctx:VxV)

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@196
PS1, Line 196:   }
please, no spaces at the start of a line

https://review.coreboot.org/#/c/28604/1/src/soc/sifive/fu540/ux00ddr.h@197
PS1, Line 197:   return (0);
please, no spaces at the start of a line

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: I71043ce9e458e25e64da28d53cd36b02d2e22acc
Gerrit-Change-Number: 28604
Gerrit-PatchSet: 1
Gerrit-Owner: Philipp Hug <philipp at hug.cx>
Gerrit-Reviewer: Ronald G. Minnich <rminnich at gmail.com>
Gerrit-CC: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-Comment-Date: Fri, 14 Sep 2018 09:54:42 +0000
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