[coreboot-gerrit] Change in coreboot[master]: soc/sifive/fu540: Update clock settings according SiFive bootloader

[Philipp Hug (Code Review)]

Hello build bot (Jenkins), 

I'd like you to reexamine a change. Please visit

    https://review.coreboot.org/28582

to look at the new patch set (#3).

Change subject: soc/sifive/fu540: Update clock settings according SiFive bootloader
......................................................................

soc/sifive/fu540: Update clock settings according SiFive bootloader

The documentation unfortunately doesn't match what SiFive uses in their FSBL.
Use the same values as in FSBL to make DDR RAM work.

Change-Id: I844cc41ed197333adeae495e71ea70b4a9603650
Signed-off-by: Philipp Hug <philipp at hug.cx>
---
M src/soc/sifive/fu540/clock.c
1 file changed, 30 insertions(+), 8 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/28582/3
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I844cc41ed197333adeae495e71ea70b4a9603650
Gerrit-Change-Number: 28582
Gerrit-PatchSet: 3
Gerrit-Owner: Philipp Hug <philipp at hug.cx>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
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