[coreboot-gerrit] Change in coreboot[master]: amd/stoneyridge: Construct BERT region from machine check
Marshall Dawson (Code Review)
gerrit at coreboot.org
Tue Sep 4 22:07:03 CEST 2018
Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/28477
Change subject: amd/stoneyridge: Construct BERT region from machine check
......................................................................
amd/stoneyridge: Construct BERT region from machine check
Add functions to build a Boot Error Record Table region based on
settings found in the MCA registers.
Two entries are reported for each error due to the nature of the ACPI
driver. The first is a Generic Processor Error, which the OS recognizes
and parses. Generic errors cannot convey much error description or
processor context. Therefore an IA32/X64 Processor Error is also added,
which allows reporting the values found in the MCA MSR registers.
Follow-on work could decode the MC errors more precisely, and better
completing the Generic Error and the Check structure. The current
level of support is sufficient to identify a (i.e., human readable)
problem in dmesg, and provides adequate context information for
analysis.
BUG=b:65446699
TEST=inspect BERT region, and dmesg, on full patch stack. Use test
data plus a failing Grunt system.
Change-Id: I4d4ce29ddefa22aa29e6d3184f1adeaea1d5f837
Signed-off-by: Marshall Dawson <marshalldawson3rd at gmail.com>
---
M src/soc/amd/stoneyridge/mca.c
1 file changed, 135 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/28477/1
diff --git a/src/soc/amd/stoneyridge/mca.c b/src/soc/amd/stoneyridge/mca.c
index bcaa927..81d95fb 100644
--- a/src/soc/amd/stoneyridge/mca.c
+++ b/src/soc/amd/stoneyridge/mca.c
@@ -19,8 +19,11 @@
#include <soc/cpu.h>
#include <soc/northbridge.h>
#include <console/console.h>
+#include <arch/bert_storage.h>
+#include <cper.h>
struct mca_bank {
+ int bank;
msr_t ctl;
msr_t sts;
msr_t addr;
@@ -28,6 +31,135 @@
msr_t cmask;
};
+static inline size_t mca_report_size_reqd(void)
+{
+ size_t size;
+
+ size = sizeof(acpi_generic_error_status_t);
+
+ size += sizeof(acpi_hest_generic_data_v300_t);
+ size += sizeof(cper_proc_generic_error_section_t);
+
+ size += sizeof(acpi_hest_generic_data_v300_t);
+ size += sizeof(cper_ia32x64_proc_error_section_t);
+
+ /* Check Error */
+ size += 1 * cper_ia32x64_check_sz();
+
+ /* Context of MCG_CAP, MCG_STAT, MCG_CTL */
+ size += cper_ia32x64_ctx_sz_bytype(CPER_IA32X64_CTX_MSR, 3);
+
+ /* Context of MCi_CTL, MCi_STATUS, MCi_ADDR, MCi_MISC */
+ size += cper_ia32x64_ctx_sz_bytype(CPER_IA32X64_CTX_MSR, 4);
+
+ /* Context of CTL_MASK */
+ size += cper_ia32x64_ctx_sz_bytype(CPER_IA32X64_CTX_MSR, 1);
+
+ return size;
+}
+
+static enum cper_x86_check_type error_to_chktype(struct mca_bank *mci)
+{
+ int error = mca_err_type(mci->sts);
+
+ if (error == MCA_ERRTYPE_BUS)
+ return X86_PROCESSOR_BUS_CHK;
+ if (error == MCA_ERRTYPE_INT)
+ return X86_PROCESSOR_MS_CHK;
+ if (error == MCA_ERRTYPE_MEM)
+ return X86_PROCESSOR_CACHE_CHK;
+ if (error == MCA_ERRTYPE_TLB)
+ return X86_PROCESSOR_TLB_CHK;
+
+ return X86_PROCESSOR_MS_CHK; /* MCA_ERRTYPE_INT and unrecognized */
+}
+
+/* Fill additional information in the Generic Processor Error Section. */
+static void fill_generic_section(cper_proc_generic_error_section_t *sec,
+ struct mca_bank *mci)
+{
+ int type = mca_err_type(mci->sts);
+
+ if (type == MCA_ERRTYPE_BUS) /* try to map MCA errors to CPER types */
+ sec->error_type = GENPROC_ERRTYPE_BUS;
+ else if (type == MCA_ERRTYPE_INT)
+ sec->error_type = GENPROC_ERRTYPE_UARCH;
+ else if (type == MCA_ERRTYPE_MEM)
+ sec->error_type = GENPROC_ERRTYPE_CACHE;
+ else if (type == MCA_ERRTYPE_TLB)
+ sec->error_type = GENPROC_ERRTYPE_TLB;
+ else
+ sec->error_type = GENPROC_ERRTYPE_UNKNOWN;
+ sec->validation |= GENPROC_VALID_PROC_ERR_TYPE;
+
+ /* Potentially also try to decode and add the type of operation, target
+ * address, requestor and responder identifiers, and instruction
+ * pointer.
+ */
+}
+
+/* Convert an error reported by an MCA bank into BERT information to be reported
+ * by the OS. The ACPI driver doesn't recognize/parse the IA32/X64 structure,
+ * which is the best method to report MSR context. As a result, add two
+ * structures: A "processor generic error" that is parsed, and an IA32/X64 one
+ * to capture complete information.
+ */
+static void build_bert_mca_error(struct mca_bank *mci)
+{
+ acpi_generic_error_status_t *status;
+ acpi_hest_generic_data_v300_t *gen_entry;
+ acpi_hest_generic_data_v300_t *x86_entry;
+ cper_proc_generic_error_section_t *gen_sec;
+ cper_ia32x64_proc_error_section_t *x86_sec;
+ cper_ia32x64_proc_error_info_t *chk;
+ cper_ia32x64_context_t *ctx;
+
+ if (!IS_ENABLED(CONFIG_ACPI_BERT))
+ return;
+
+ if (mca_report_size_reqd() > bert_storage_remaining())
+ goto failed;
+
+ status = bert_new_event(&CPER_SEC_PROC_GENERIC_GUID);
+ if (!status)
+ goto failed;
+
+ gen_entry = acpi_hest_generic_data3(status);
+ gen_sec = section_of_acpientry(gen_sec, gen_entry);
+
+ fill_generic_section(gen_sec, mci);
+
+ x86_entry = bert_append_ia32x64(status);
+ x86_sec = section_of_acpientry(x86_sec, x86_entry);
+
+ chk = new_cper_ia32x64_check(status, x86_sec, error_to_chktype(mci));
+ if (!chk)
+ goto failed;
+ /* Future work may interpret the specific Family 15h error symptoms
+ * in the MCA registers and enhance the fields reported within the
+ * Error Check just created. The level of reporting by the ACPI
+ * driver doesn't currently reward that level of detail.
+ */
+
+ ctx = cper_new_ia32x64_context_msr(status, x86_sec, MCG_CAP, 3);
+ if (!ctx)
+ goto failed;
+ ctx = cper_new_ia32x64_context_msr(status, x86_sec,
+ MC0_CTL + (mci->bank * 4), 4);
+ if (!ctx)
+ goto failed;
+ ctx = cper_new_ia32x64_context_msr(status, x86_sec,
+ MC0_CTL_MASK + mci->bank, 1);
+ if (!ctx)
+ goto failed;
+
+ return;
+
+failed:
+ /* We're here because of a hardware error, don't break something else */
+ printk(BIOS_ERR, "Error, not enough room in reserved BERT region for #MC error\n");
+}
+
static const char *const mca_bank_name[] = {
"Load-store unit",
"Instruction fetch unit",
@@ -74,6 +206,9 @@
mci.cmask = rdmsr(MC0_CTL_MASK + i);
printk(BIOS_WARNING, " MC%d_CTL_MASK = %08x_%08x\n",
i, mci.cmask.hi, mci.cmask.lo);
+
+ mci.bank = i;
+ build_bert_mca_error(&mci);
}
}
}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I4d4ce29ddefa22aa29e6d3184f1adeaea1d5f837
Gerrit-Change-Number: 28477
Gerrit-PatchSet: 1
Gerrit-Owner: Marshall Dawson <marshalldawson3rd at gmail.com>
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