[coreboot-gerrit] Change in coreboot[master]: riscv: update misaligned memory access exception handling

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27972 )

Change subject: riscv: update misaligned memory access exception handling
......................................................................


Patch Set 31:

(1 comment)

https://review.coreboot.org/#/c/27972/31/src/arch/riscv/misaligend.c
File src/arch/riscv/misaligend.c:

https://review.coreboot.org/#/c/27972/31/src/arch/riscv/misaligend.c@165
PS31, Line 165: 		if (EXTRACT_FIELD(ins, 0x1c) != 0x7)) {
trailing statements should be on next line



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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: I9983d56245eab1d458a84cb1432aeb805df7a49f
Gerrit-Change-Number: 27972
Gerrit-PatchSet: 31
Gerrit-Owner: Xiang Wang <wxjstz at 126.com>
Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: Philipp Hug <philipp at hug.cx>
Gerrit-Reviewer: Ronald G. Minnich <rminnich at gmail.com>
Gerrit-Reviewer: Shawn Chang <citypw at gmail.com>
Gerrit-Reviewer: Xiang Wang <wxjstz at 126.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-Reviewer: ron minnich (1001188)
Gerrit-Comment-Date: Sat, 01 Sep 2018 15:19:03 +0000
Gerrit-HasComments: Yes
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