[coreboot-gerrit] Change in coreboot[master]: cpu/intel/haswell: Allow use of TSC for the monotonic timer

[Tristan Corrick (Code Review)]

Tristan Corrick has uploaded this change for review. ( https://review.coreboot.org/29383


Change subject: cpu/intel/haswell: Allow use of TSC for the monotonic timer
......................................................................

cpu/intel/haswell: Allow use of TSC for the monotonic timer

When the Haswell-specific monotonic timer is used on an ASRock H81M-HDS
with a Pentium G3258, the following exception is generated, causing the
system to hang.

	CPU Index 0 - APIC 0 Unexpected Exception:13 @ 10:7f7a3736 - Halting
	Code: 0 eflags: 00010006 cr2: 00000000
	eax: 00262626 ebx: 00140000 ecx: 00000603 edx: 00360000
	edi: 00000007 esi: 00262626 ebp: 7f7c0fd8 esp: 7f7c0e90

The exception occurs when trying to read `MSR_COUNTER_24_MHz`, located
at 0x637. This MSR doesn't seem to be publicly documented, and also
doesn't seem to exist on the Pentium G3258. It possibly only exists on
Haswell-ULT CPUs.

So, allow boards to use the TSC monotonic timer instead. They can do
this by placing `select TSC_MONOTONIC_TIMER` in the mainboard Kconfig.

Change-Id: I31d0e801b8cc85330dcb70c3fc03670f2e677e8f
Signed-off-by: Tristan Corrick <tristan at corrick.kiwi>
---
M src/cpu/intel/haswell/Makefile.inc
1 file changed, 4 insertions(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/29383/1

diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc
index bbd98da..c317c09 100644
--- a/src/cpu/intel/haswell/Makefile.inc
+++ b/src/cpu/intel/haswell/Makefile.inc
@@ -7,14 +7,17 @@
 ramstage-y += acpi.c
 ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
 ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c
-ramstage-y += monotonic_timer.c
 
 romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
 postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c
+
+ifneq ($(CONFIG_TSC_MONOTONIC_TIMER),y)
+ramstage-y += monotonic_timer.c
 smm-y += monotonic_timer.c
+endif
 
 cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S
 postcar-y += ../car/non-evict/exit_car.S

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I31d0e801b8cc85330dcb70c3fc03670f2e677e8f
Gerrit-Change-Number: 29383
Gerrit-PatchSet: 1
Gerrit-Owner: Tristan Corrick <tristan at corrick.kiwi>
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