[coreboot-gerrit] Change in coreboot[master]: soc/intel/fsp_broadwell_de: Add additional UPDs

[Philipp Deppenwiese (Code Review)]

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/29323


Change subject: soc/intel/fsp_broadwell_de: Add additional UPDs
......................................................................

soc/intel/fsp_broadwell_de: Add additional UPDs

* Add MemScrambling and MemEccSupport options.

Change-Id: I2687a52d4fa6f88d1a5fb5e83cc02419d688f6b4
Signed-off-by: Philipp Deppenwiese <zaolin at das-labor.org>
---
M src/soc/intel/fsp_broadwell_de/fsp/Kconfig
M src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c
2 files changed, 27 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/29323/1

diff --git a/src/soc/intel/fsp_broadwell_de/fsp/Kconfig b/src/soc/intel/fsp_broadwell_de/fsp/Kconfig
index 32fe0b8..1beb264 100644
--- a/src/soc/intel/fsp_broadwell_de/fsp/Kconfig
+++ b/src/soc/intel/fsp_broadwell_de/fsp/Kconfig
@@ -102,6 +102,17 @@
 	help
 	  Path to the file which contains the SPD data for Channel 1, DIMM 1.
 
+config FSP_MEMORY_SCRAMBLING
+	bool "Enable Memory Scrambling"
+	default n
+	help
+	  Enable data scrambling of memory during ram initialization.
+	  See https://en.wikipedia.org/wiki/Memory_controller#Security
+
+config FSP_MEMORY_ECC_SUPPORT
+	bool "Enable ECC Memory support"
+	default y
+
 config FSP_HYPERTHREADING
 	bool "Enable Hyper-Threading"
 	default y
diff --git a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c
index 800f686..7fe3f21 100644
--- a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c
+++ b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c
@@ -91,6 +91,22 @@
 		UpdData->MemDownEnable ? "Enabled" : "Disabled");
 
 	/*
+	 * Memory Scrambling
+	 */
+	if (IS_ENABLED(CONFIG_FSP_MEMORY_SCRAMBLING))
+		UpdData->MemScrambling = 1;
+	else
+		UpdData->MemScrambling = 0;
+
+	/*
+	 * Memory ECC support
+	 */
+	if (IS_ENABLED(CONFIG_FSP_MEMORY_ECC_SUPPORT))
+		UpdData->MemEccSupport = 1;
+	else
+		UpdData->MemEccSupport = 0;
+
+	/*
 	 * Fast Boot
 	 */
 	if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE))

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I2687a52d4fa6f88d1a5fb5e83cc02419d688f6b4
Gerrit-Change-Number: 29323
Gerrit-PatchSet: 1
Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki at gmail.com>
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