[coreboot-gerrit] Change in coreboot[master]: src: Remove unneeded whitespace
build bot (Jenkins) (Code Review)
gerrit at coreboot.org
Wed Oct 17 12:52:42 CEST 2018
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29161 )
Change subject: src: Remove unneeded whitespace
......................................................................
Patch Set 5:
(98 comments)
https://review.coreboot.org/#/c/29161/5/src/cpu/amd/family_10h-family_15h/fidvid.c
File src/cpu/amd/family_10h-family_15h/fidvid.c:
https://review.coreboot.org/#/c/29161/5/src/cpu/amd/family_10h-family_15h/fidvid.c@499
PS5, Line 499: if (cpuRev & (AMD_DA_Cx | AMD_RB_C3)) {
braces {} are not necessary for single statement blocks
https://review.coreboot.org/#/c/29161/5/src/cpu/amd/family_10h-family_15h/fidvid.c@504
PS5, Line 504: if ((procPkg == AMD_PKGTYPE_G34) || (procPkg == AMD_PKGTYPE_C32)) {
braces {} are not necessary for single statement blocks
https://review.coreboot.org/#/c/29161/5/src/cpu/amd/family_10h-family_15h/fidvid.c@667
PS5, Line 667: if ((((u32)0xffffffff) - initial_msr.lo) < corrected_timeout) {
braces {} are not necessary for single statement blocks
https://review.coreboot.org/#/c/29161/5/src/cpu/amd/family_10h-family_15h/fidvid.c@676
PS5, Line 676: || ((tsc_msr.hi == timeout.hi) && (tsc_msr.lo > timeout.lo));
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/cpu/amd/family_10h-family_15h/fidvid.c@843
PS5, Line 843: vid_max = (reg1fc & SINGLE_PLANE_NB_VID_MASK) >> SINGLE_PLANE_NB_VID_SHIFT;
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/cpu/amd/family_10h-family_15h/fidvid.c@844
PS5, Line 844: fid_max = (reg1fc & SINGLE_PLANE_NB_FID_MASK) >> SINGLE_PLANE_NB_FID_SHIFT;
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/cpu/amd/family_10h-family_15h/fidvid.c@847
PS5, Line 847: vid_max = vid_max - ((reg1fc & DUAL_PLANE_NB_VID_OFF_MASK) >> DUAL_PLANE_NB_VID_SHIFT);
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/cpu/amd/family_10h-family_15h/fidvid.c@848
PS5, Line 848: fid_max = fid_max + ((reg1fc & DUAL_PLANE_NB_FID_OFF_MASK) >> DUAL_PLANE_NB_FID_SHIFT);
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/cpu/amd/family_10h-family_15h/powernow_acpi.c
File src/cpu/amd/family_10h-family_15h/powernow_acpi.c:
https://review.coreboot.org/#/c/29161/5/src/cpu/amd/family_10h-family_15h/powernow_acpi.c@229
PS5, Line 229: * Based on the CPU socket type, cmp_cap and pwr_lmt, get the power limit.
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/cpu/via/nano/nano_init.c
File src/cpu/via/nano/nano_init.c:
https://review.coreboot.org/#/c/29161/5/src/cpu/via/nano/nano_init.c@125
PS5, Line 125: msr.lo |= ((1 << 25) | (1 << 26) | (1 << 31)); /* C1e, C2e, C3e */
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c
File src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c:
https://review.coreboot.org/#/c/29161/5/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c@145
PS5, Line 145: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/mainboard/amd/lamar/BiosCallOuts.c
File src/mainboard/amd/lamar/BiosCallOuts.c:
https://review.coreboot.org/#/c/29161/5/src/mainboard/amd/lamar/BiosCallOuts.c@162
PS5, Line 162: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/mainboard/amd/olivehill/BiosCallOuts.c
File src/mainboard/amd/olivehill/BiosCallOuts.c:
https://review.coreboot.org/#/c/29161/5/src/mainboard/amd/olivehill/BiosCallOuts.c@114
PS5, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/mainboard/amd/olivehillplus/BiosCallOuts.c
File src/mainboard/amd/olivehillplus/BiosCallOuts.c:
https://review.coreboot.org/#/c/29161/5/src/mainboard/amd/olivehillplus/BiosCallOuts.c@128
PS5, Line 128: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/mainboard/amd/parmer/BiosCallOuts.c
File src/mainboard/amd/parmer/BiosCallOuts.c:
https://review.coreboot.org/#/c/29161/5/src/mainboard/amd/parmer/BiosCallOuts.c@114
PS5, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c
File src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c:
https://review.coreboot.org/#/c/29161/5/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c@109
PS5, Line 109: current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 5);
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c
File src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c:
https://review.coreboot.org/#/c/29161/5/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c@147
PS5, Line 147: for (i = 1; i< sysconf.hc_possible_num; i++) {
spaces required around that '<' (ctx:VxW)
https://review.coreboot.org/#/c/29161/5/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
File src/mainboard/amd/serengeti_cheetah_fam10/mptable.c:
https://review.coreboot.org/#/c/29161/5/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c@110
PS5, Line 110: for (i = 0; i < 4; i++) {
braces {} are not necessary for single statement blocks
https://review.coreboot.org/#/c/29161/5/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c@116
PS5, Line 116: for (i = 0; i < 4; i++) {
braces {} are not necessary for single statement blocks
https://review.coreboot.org/#/c/29161/5/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c@122
PS5, Line 122: for (i = 0; i < 4; i++) {
braces {} are not necessary for single statement blocks
https://review.coreboot.org/#/c/29161/5/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c@128
PS5, Line 128: for (i = 0; i < 4; i++) {
braces {} are not necessary for single statement blocks
https://review.coreboot.org/#/c/29161/5/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c@150
PS5, Line 150: for (ii = 0; ii < 4; ii++) {
Too many leading tabs - consider code refactoring
https://review.coreboot.org/#/c/29161/5/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c@150
PS5, Line 150: for (ii = 0; ii < 4; ii++) {
braces {} are not necessary for single statement blocks
https://review.coreboot.org/#/c/29161/5/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c@163
PS5, Line 163: for (ii = 0; ii < 4; ii++) {
Too many leading tabs - consider code refactoring
https://review.coreboot.org/#/c/29161/5/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c@163
PS5, Line 163: for (ii = 0; ii < 4; ii++) {
braces {} are not necessary for single statement blocks
https://review.coreboot.org/#/c/29161/5/src/mainboard/amd/thatcher/BiosCallOuts.c
File src/mainboard/amd/thatcher/BiosCallOuts.c:
https://review.coreboot.org/#/c/29161/5/src/mainboard/amd/thatcher/BiosCallOuts.c@114
PS5, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/mainboard/amd/torpedo/gpio.c
File src/mainboard/amd/torpedo/gpio.c:
https://review.coreboot.org/#/c/29161/5/src/mainboard/amd/torpedo/gpio.c@94
PS5, Line 94: if (BoardType == 0) {
braces {} are not necessary for single statement blocks
https://review.coreboot.org/#/c/29161/5/src/mainboard/bap/ode_e20XX/BiosCallOuts.c
File src/mainboard/bap/ode_e20XX/BiosCallOuts.c:
https://review.coreboot.org/#/c/29161/5/src/mainboard/bap/ode_e20XX/BiosCallOuts.c@117
PS5, Line 117: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/mainboard/bap/ode_e21XX/BiosCallOuts.c
File src/mainboard/bap/ode_e21XX/BiosCallOuts.c:
https://review.coreboot.org/#/c/29161/5/src/mainboard/bap/ode_e21XX/BiosCallOuts.c@130
PS5, Line 130: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/mainboard/biostar/a68n_5200/BiosCallOuts.c
File src/mainboard/biostar/a68n_5200/BiosCallOuts.c:
https://review.coreboot.org/#/c/29161/5/src/mainboard/biostar/a68n_5200/BiosCallOuts.c@114
PS5, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/mainboard/gizmosphere/gizmo/OemCustomize.c
File src/mainboard/gizmosphere/gizmo/OemCustomize.c:
https://review.coreboot.org/#/c/29161/5/src/mainboard/gizmosphere/gizmo/OemCustomize.c@126
PS5, Line 126: HW_RXEN_SEED(ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED),
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c
File src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c:
https://review.coreboot.org/#/c/29161/5/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c@114
PS5, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c
File src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c:
https://review.coreboot.org/#/c/29161/5/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c@115
PS5, Line 115: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/mainboard/lenovo/g505s/BiosCallOuts.c
File src/mainboard/lenovo/g505s/BiosCallOuts.c:
https://review.coreboot.org/#/c/29161/5/src/mainboard/lenovo/g505s/BiosCallOuts.c@115
PS5, Line 115: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/mainboard/lenovo/t60/smihandler.c
File src/mainboard/lenovo/t60/smihandler.c:
https://review.coreboot.org/#/c/29161/5/src/mainboard/lenovo/t60/smihandler.c@52
PS5, Line 52: printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar, *(bar+LVTMA_BL_MOD_LEVEL));
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/mainboard/lenovo/z61t/smihandler.c
File src/mainboard/lenovo/z61t/smihandler.c:
https://review.coreboot.org/#/c/29161/5/src/mainboard/lenovo/z61t/smihandler.c@53
PS5, Line 53: printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar,
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/mainboard/lippert/frontrunner-af/mainboard.c
File src/mainboard/lippert/frontrunner-af/mainboard.c:
https://review.coreboot.org/#/c/29161/5/src/mainboard/lippert/frontrunner-af/mainboard.c@68
PS5, Line 68: FCH_IOMUX(50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/mainboard/lippert/frontrunner-af/mainboard.c@69
PS5, Line 69: FCH_GPIO (50) = 0xC0; // = output set to 1 as it's never needed
space prohibited between function name and open parenthesis '('
https://review.coreboot.org/#/c/29161/5/src/mainboard/lippert/frontrunner-af/mainboard.c@72
PS5, Line 72: FCH_GPIO (56) = 0x28; // = inputs, disable int. pull-ups
space prohibited between function name and open parenthesis '('
https://review.coreboot.org/#/c/29161/5/src/mainboard/lippert/frontrunner-af/mainboard.c@74
PS5, Line 74: FCH_GPIO (57) = 0x28;
space prohibited between function name and open parenthesis '('
https://review.coreboot.org/#/c/29161/5/src/mainboard/lippert/frontrunner-af/mainboard.c@76
PS5, Line 76: FCH_GPIO (58) = 0x28;
space prohibited between function name and open parenthesis '('
https://review.coreboot.org/#/c/29161/5/src/mainboard/lippert/frontrunner-af/mainboard.c@77
PS5, Line 77: FCH_IOMUX(96) = 1; // "Gpio96": GEVENT0# signal on X2 connector (int. PU)
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/mainboard/lippert/frontrunner-af/mainboard.c@78
PS5, Line 78: FCH_IOMUX(52) = 1; // GPIO52,61,62,187-192 free to use on X2 connector
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/mainboard/lippert/toucan-af/mainboard.c
File src/mainboard/lippert/toucan-af/mainboard.c:
https://review.coreboot.org/#/c/29161/5/src/mainboard/lippert/toucan-af/mainboard.c@36
PS5, Line 36: FCH_IOMUX(50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/mainboard/lippert/toucan-af/mainboard.c@37
PS5, Line 37: FCH_GPIO (50) = 0xC0; // = output set to 1 as it's never needed
space prohibited between function name and open parenthesis '('
https://review.coreboot.org/#/c/29161/5/src/mainboard/lippert/toucan-af/mainboard.c@41
PS5, Line 41: FCH_GPIO (56) = 0x28; // = inputs, disable int. pull-ups
space prohibited between function name and open parenthesis '('
https://review.coreboot.org/#/c/29161/5/src/mainboard/lippert/toucan-af/mainboard.c@43
PS5, Line 43: FCH_GPIO (57) = 0x28;
space prohibited between function name and open parenthesis '('
https://review.coreboot.org/#/c/29161/5/src/mainboard/lippert/toucan-af/mainboard.c@45
PS5, Line 45: FCH_GPIO (58) = 0x28;
space prohibited between function name and open parenthesis '('
https://review.coreboot.org/#/c/29161/5/src/mainboard/msi/ms9652_fam10/get_bus_conf.c
File src/mainboard/msi/ms9652_fam10/get_bus_conf.c:
https://review.coreboot.org/#/c/29161/5/src/mainboard/msi/ms9652_fam10/get_bus_conf.c@104
PS5, Line 104: dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0));
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/mainboard/msi/ms9652_fam10/get_bus_conf.c@109
PS5, Line 109: printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2);
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/mainboard/pcengines/apu1/OemCustomize.c
File src/mainboard/pcengines/apu1/OemCustomize.c:
https://review.coreboot.org/#/c/29161/5/src/mainboard/pcengines/apu1/OemCustomize.c@111
PS5, Line 111: HW_RXEN_SEED(ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED),
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/mainboard/pcengines/apu2/mainboard.c
File src/mainboard/pcengines/apu2/mainboard.c:
https://review.coreboot.org/#/c/29161/5/src/mainboard/pcengines/apu2/mainboard.c@175
PS5, Line 175: pm_write16(PM_S_STATE_CONTROL, pm_read16(PM_S_STATE_CONTROL) | (1 << 14));
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c
File src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c:
https://review.coreboot.org/#/c/29161/5/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c@102
PS5, Line 102: dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0));
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c@107
PS5, Line 107: printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2);
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c
File src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c:
https://review.coreboot.org/#/c/29161/5/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c@108
PS5, Line 108: dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0));
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c@113
PS5, Line 113: printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2);
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/mainboard/tyan/s2912_fam10/get_bus_conf.c
File src/mainboard/tyan/s2912_fam10/get_bus_conf.c:
https://review.coreboot.org/#/c/29161/5/src/mainboard/tyan/s2912_fam10/get_bus_conf.c@101
PS5, Line 101: dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0));
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/mainboard/tyan/s2912_fam10/get_bus_conf.c@106
PS5, Line 106: printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2);
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/northbridge/amd/agesa/family12/dimmSpd.c
File src/northbridge/amd/agesa/family12/dimmSpd.c:
https://review.coreboot.org/#/c/29161/5/src/northbridge/amd/agesa/family12/dimmSpd.c@58
PS5, Line 58: )
please, no spaces at the start of a line
https://review.coreboot.org/#/c/29161/5/src/northbridge/intel/fsp_rangeley/northbridge.c
File src/northbridge/intel/fsp_rangeley/northbridge.c:
https://review.coreboot.org/#/c/29161/5/src/northbridge/intel/fsp_rangeley/northbridge.c@134
PS5, Line 134: ram_resource(dev, index++, 0x100000000 >> 10, (bmbound_hi - 0x100000000) >> 10);
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/soc/broadcom/cygnus/ddr_init.c
File src/soc/broadcom/cygnus/ddr_init.c:
https://review.coreboot.org/#/c/29161/5/src/soc/broadcom/cygnus/ddr_init.c@74
PS5, Line 74: reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL, (readvalue & ~(1 << DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__RX_MODE_R)));
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/soc/broadcom/cygnus/ddr_init.c@78
PS5, Line 78: reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_ZQ_CAL, (readvalue & ~(1 << DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_IDDQ)));
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/soc/broadcom/cygnus/ddr_init.c@82
PS5, Line 82: reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, (readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDLE)));
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/soc/broadcom/cygnus/ddr_init.c@85
PS5, Line 85: reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, (readvalue & 0xffff800f));
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/soc/broadcom/cygnus/ddr_init.c@88
PS5, Line 88: reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, (readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDDQ)));
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/soc/broadcom/cygnus/ddr_init.c@92
PS5, Line 92: reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, (readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDLE)));
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/soc/broadcom/cygnus/ddr_init.c@95
PS5, Line 95: reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, (readvalue & 0xffff800f));
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/soc/broadcom/cygnus/ddr_init.c@98
PS5, Line 98: reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, (readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDDQ)));
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/soc/broadcom/cygnus/ddr_init.c@146
PS5, Line 146: #define SET_OVR_STEP(v) (0x30000 | ((v) & 0x3F)) /* OVR_FORCE = OVR_EN = 1, OVR_STEP = v */
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/soc/broadcom/cygnus/ddr_init.c@452
PS5, Line 452: reg32_write((volatile uint32_t *)DDR_DENALI_CTL_43, (1 << 17) | (1 << 24) | (1 << 25));
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/soc/broadcom/cygnus/ddr_init.c@458
PS5, Line 458: if (reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18)) {
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/soc/broadcom/cygnus/ddr_init.c@458
PS5, Line 458: if (reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18)) {
braces {} are not necessary for single statement blocks
https://review.coreboot.org/#/c/29161/5/src/soc/broadcom/cygnus/ddr_init.c@464
PS5, Line 464: if (j == 0 && (reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18)) == 0) {
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/soc/broadcom/cygnus/ddr_init.c@968
PS5, Line 968: if ((((uint32_t)reg >= DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN) && ((uint32_t)reg <= (DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN + 0x114)))
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/soc/broadcom/cygnus/ddr_init.c@986
PS5, Line 986: if (CONFIG_SHMOO_REUSE_MEMTEST_LENGTH > 0) {
please, no spaces at the start of a line
https://review.coreboot.org/#/c/29161/5/src/soc/broadcom/cygnus/ddr_init.c@1121
PS5, Line 1121: for (i = 0; i < 1000; i++);
please, no spaces at the start of a line
https://review.coreboot.org/#/c/29161/5/src/soc/broadcom/cygnus/ddr_init.c@1121
PS5, Line 1121: for (i = 0; i < 1000; i++);
trailing statements should be on next line
https://review.coreboot.org/#/c/29161/5/src/soc/broadcom/cygnus/ddr_init.c@1381
PS5, Line 1381: printk(BIOS_INFO, "PHY revision version: 0x%08x\n", val);
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/soc/broadcom/cygnus/phy_reg_access.c
File src/soc/broadcom/cygnus/phy_reg_access.c:
https://review.coreboot.org/#/c/29161/5/src/soc/broadcom/cygnus/phy_reg_access.c@20
PS5, Line 20: data = (* (volatile uint32 *) (((uint32)GLOBAL_REG_RBUS_START) | (address)));
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/soc/broadcom/cygnus/phy_reg_access.c@27
PS5, Line 27: ((* (volatile uint32 *) (((uint32)GLOBAL_REG_RBUS_START) | (address))) = data);
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/soc/intel/baytrail/perf_power.c
File src/soc/intel/baytrail/perf_power.c:
https://review.coreboot.org/#/c/29161/5/src/soc/intel/baytrail/perf_power.c@224
PS5, Line 224: E(CCU, 0x1c, MASK_VAL(1, 0, 0x0)), //vlv.ccu.clkgate_en_1.lps_free_clkgate_en
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/soc/intel/fsp_baytrail/northcluster.c
File src/soc/intel/fsp_baytrail/northcluster.c:
https://review.coreboot.org/#/c/29161/5/src/soc/intel/fsp_baytrail/northcluster.c@161
PS5, Line 161: ram_resource(dev, index++, 0x100000000 >> 10, highmem_size >> 10);
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/southbridge/amd/cimx/sb800/fan.c
File src/southbridge/amd/cimx/sb800/fan.c:
https://review.coreboot.org/#/c/29161/5/src/southbridge/amd/cimx/sb800/fan.c@234
PS5, Line 234: sb_config.Pecstruct.MSGFun89zone0MSGREG2 = (sb_chip->imc_tempin0_at & 0xff);
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/southbridge/amd/cimx/sb800/fan.c@238
PS5, Line 238: sb_config.Pecstruct.MSGFun89zone0MSGREG6 = (sb_chip->imc_tempin0_ct & 0xff);
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/southbridge/amd/cimx/sb800/fan.c@252
PS5, Line 252: sb_config.Pecstruct.MSGFun89zone1MSGREG2 = (sb_chip->imc_tempin1_at & 0xff);
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/southbridge/amd/cimx/sb800/fan.c@256
PS5, Line 256: sb_config.Pecstruct.MSGFun89zone1MSGREG6 = (sb_chip->imc_tempin1_ct & 0xff);
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/southbridge/amd/cimx/sb800/fan.c@270
PS5, Line 270: sb_config.Pecstruct.MSGFun89zone2MSGREG2 = (sb_chip->imc_tempin2_at & 0xff);
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/southbridge/amd/cimx/sb800/fan.c@274
PS5, Line 274: sb_config.Pecstruct.MSGFun89zone2MSGREG6 = (sb_chip->imc_tempin2_ct & 0xff);
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/southbridge/amd/cimx/sb800/fan.c@288
PS5, Line 288: sb_config.Pecstruct.MSGFun89zone3MSGREG2 = (sb_chip->imc_tempin3_at & 0xff);
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/southbridge/amd/cimx/sb800/fan.c@292
PS5, Line 292: sb_config.Pecstruct.MSGFun89zone3MSGREG6 = (sb_chip->imc_tempin3_ct & 0xff);
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/southbridge/amd/rs780/gfx.c
File src/southbridge/amd/rs780/gfx.c:
https://review.coreboot.org/#/c/29161/5/src/southbridge/amd/rs780/gfx.c@250
PS5, Line 250: if (Attribute & MMIO_ATTRIB_NP_ONLY && pMMIO[k].Attribute == 0) {
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/southbridge/amd/rs780/gfx.c@250
PS5, Line 250: if (Attribute & MMIO_ATTRIB_NP_ONLY && pMMIO[k].Attribute == 0) {
braces {} are not necessary for single statement blocks
https://review.coreboot.org/#/c/29161/5/src/southbridge/amd/sb700/sata.c
File src/southbridge/amd/sb700/sata.c:
https://review.coreboot.org/#/c/29161/5/src/southbridge/amd/sb700/sata.c@473
PS5, Line 473: (i % 2) ? "Slave" : "Master", i);
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/southbridge/amd/sr5650/pcie.c
File src/southbridge/amd/sr5650/pcie.c:
https://review.coreboot.org/#/c/29161/5/src/southbridge/amd/sr5650/pcie.c@809
PS5, Line 809: if (!((pci_read_config32(dev, 0x6C) >> 6) & 0x01)) {
braces {} are not necessary for single statement blocks
https://review.coreboot.org/#/c/29161/5/src/southbridge/intel/bd82x6x/early_usb.c
File src/southbridge/intel/bd82x6x/early_usb.c:
https://review.coreboot.org/#/c/29161/5/src/southbridge/intel/bd82x6x/early_usb.c@38
PS5, Line 38: pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI BAR */
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/southbridge/intel/fsp_bd82x6x/early_init.c
File src/southbridge/intel/fsp_bd82x6x/early_init.c:
https://review.coreboot.org/#/c/29161/5/src/southbridge/intel/fsp_bd82x6x/early_init.c@145
PS5, Line 145: pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI BAR */
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/southbridge/intel/fsp_i89xx/early_init.c
File src/southbridge/intel/fsp_i89xx/early_init.c:
https://review.coreboot.org/#/c/29161/5/src/southbridge/intel/fsp_i89xx/early_init.c@32
PS5, Line 32: pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI BAR */
line over 80 characters
https://review.coreboot.org/#/c/29161/5/src/southbridge/nvidia/ck804/early_setup.c
File src/southbridge/nvidia/ck804/early_setup.c:
https://review.coreboot.org/#/c/29161/5/src/southbridge/nvidia/ck804/early_setup.c@258
PS5, Line 258: RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xe4), ~(1 << 23), (1 << 23),
line over 80 characters
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d
Gerrit-Change-Number: 29161
Gerrit-PatchSet: 5
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-Comment-Date: Wed, 17 Oct 2018 10:52:42 +0000
Gerrit-HasComments: Yes
Gerrit-HasLabels: No
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