[coreboot-gerrit] Change in coreboot[master]: drivers/intel/fsp*: Use newly added post codes for memory param prep

[Furquan Shaikh (Code Review)]

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/29151


Change subject: drivers/intel/fsp*: Use newly added post codes for memory param prep
......................................................................

drivers/intel/fsp*: Use newly added post codes for memory param prep

This change replaces use of post codes 0x34 and 0x36 in fsp drivers to
instead use POST_MEM_PREINIT_PREP_{START,END} to make it easy to
search from where these post codes are generated during boot flow.

Additionally, it adds POST_MEM_PREINIT_PREP_END to fsp2_0 memory_init
to make it consistent with fsp1_1 memory init.

Change-Id: I307ada1679f212c424e9f7ad2c9d254e24f41fd3
Signed-off-by: Furquan Shaikh <furquan at google.com>
---
M src/drivers/intel/fsp1_1/raminit.c
M src/drivers/intel/fsp1_1/romstage.c
M src/drivers/intel/fsp2_0/memory_init.c
3 files changed, 6 insertions(+), 4 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/29151/1

diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c
index 407a0b6..bca9f71 100644
--- a/src/drivers/intel/fsp1_1/raminit.c
+++ b/src/drivers/intel/fsp1_1/raminit.c
@@ -64,7 +64,7 @@
 	 * set to NULL.  This indicates that the FSP code will use the UPD
 	 * region in the FSP binary.
 	 */
-	post_code(0x34);
+	post_code(POST_MEM_PREINIT_PREP_START);
 	fsp_header = params->chipset_context;
 	vpd_ptr = (VPD_DATA_REGION *)(fsp_header->CfgRegionOffset +
 					fsp_header->ImageBase);
@@ -103,7 +103,7 @@
 	if (IS_ENABLED(CONFIG_MMA))
 		setup_mma(&memory_init_params);
 
-	post_code(0x36);
+	post_code(POST_MEM_PREINIT_PREP_END);
 
 	/* Display the UPD data */
 	if (IS_ENABLED(CONFIG_DISPLAY_UPD_DATA))
diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c
index b239d86..8e8c24c 100644
--- a/src/drivers/intel/fsp1_1/romstage.c
+++ b/src/drivers/intel/fsp1_1/romstage.c
@@ -344,7 +344,7 @@
 /* Transition RAM from off or self-refresh to active */
 __weak void raminit(struct romstage_params *params)
 {
-	post_code(0x34);
+	post_code(POST_MEM_PREINIT_PREP_START);
 	die("ERROR - No RAM initialization specified!\n");
 }
 
diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
index dc37eaa..1026c79 100644
--- a/src/drivers/intel/fsp2_0/memory_init.c
+++ b/src/drivers/intel/fsp2_0/memory_init.c
@@ -273,7 +273,7 @@
 	FSPM_ARCH_UPD *arch_upd;
 	uint32_t fsp_version;
 
-	post_code(0x34);
+	post_code(POST_MEM_PREINIT_PREP_START);
 
 	fsp_version = fsp_memory_settings_version(hdr);
 
@@ -301,6 +301,8 @@
 	if (IS_ENABLED(CONFIG_MMA))
 		setup_mma(&fspm_upd.FspmConfig);
 
+	post_code(POST_MEM_PREINIT_PREP_END);
+
 	/* Call FspMemoryInit */
 	fsp_raminit = (void *)(hdr->image_base + hdr->memory_init_entry_offset);
 	fsp_debug_before_memory_init(fsp_raminit, upd, &fspm_upd);

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I307ada1679f212c424e9f7ad2c9d254e24f41fd3
Gerrit-Change-Number: 29151
Gerrit-PatchSet: 1
Gerrit-Owner: Furquan Shaikh <furquan at google.com>
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