[coreboot-gerrit] Change in coreboot[master]: riscv: add support smp_pause / smp_resume

[Xiang Wang (Code Review)]

Xiang Wang has posted comments on this change. ( https://review.coreboot.org/29023 )

Change subject: riscv: add support smp_pause / smp_resume
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Patch Set 8:

(1 comment)

https://review.coreboot.org/#/c/29023/7/src/arch/riscv/smp.c
File src/arch/riscv/smp.c:

https://review.coreboot.org/#/c/29023/7/src/arch/riscv/smp.c@24
PS7, Line 24: 	if (read_csr(mhartid) != working_hartid) {
> Or as an alternative: […]
Synchronous operations require atomic operations and static variables. Static variables are not easy to handle in bootblocks. Can you give me some suggestions?



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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: I6f8159637bfb15f54f0abeb335de2ba6e9cf82fb
Gerrit-Change-Number: 29023
Gerrit-PatchSet: 8
Gerrit-Owner: Xiang Wang <wxjstz at 126.com>
Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
Gerrit-Reviewer: Philipp Hug <philipp at hug.cx>
Gerrit-Reviewer: Shawn Chang <citypw at gmail.com>
Gerrit-Reviewer: Xiang Wang <wxjstz at 126.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-Comment-Date: Mon, 15 Oct 2018 13:59:25 +0000
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