[coreboot-gerrit] Change in coreboot[master]: soc/amd/stoneyridge: Remove errant parenthesis in southbridge.h
Marshall Dawson (Code Review)
gerrit at coreboot.org
Fri Oct 12 19:26:59 CEST 2018
Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/29073
Change subject: soc/amd/stoneyridge: Remove errant parenthesis in southbridge.h
......................................................................
soc/amd/stoneyridge: Remove errant parenthesis in southbridge.h
Delete an unmatched opening parenthesis in the definition for the EHCI
hub config register definition. This wasn't causing a problem unless
EHCI debug was enabled.
TEST=Jam Makefile.inc to unconditionally build enable_usbdebug.c and
verify successful build
Change-Id: I5f461d1573e416b5a8ee24329142e3c46b6a05e3
Signed-off-by: Marshall Dawson <marshalldawson3rd at gmail.com>
---
M src/soc/amd/stoneyridge/include/soc/southbridge.h
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/29073/1
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 403e980..ce0af95 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -154,7 +154,7 @@
#define EHCI_HUB_CONFIG4 0x90
#define DEBUG_PORT_SELECT_SHIFT 16
#define DEBUG_PORT_ENABLE BIT(18)
-#define DEBUG_PORT_MASK (BIT(16) | BIT(17) | (BIT(18))
+#define DEBUG_PORT_MASK (BIT(16) | BIT(17) | BIT(18))
#define WIDEIO_RANGE_ERROR -1
#define TOTAL_WIDEIO_PORTS 3
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I5f461d1573e416b5a8ee24329142e3c46b6a05e3
Gerrit-Change-Number: 29073
Gerrit-PatchSet: 1
Gerrit-Owner: Marshall Dawson <marshalldawson3rd at gmail.com>
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