[coreboot-gerrit] Change in coreboot[master]: amd/stoneyridge: Clarify XHCI_PM register definitions
Martin Roth (Code Review)
gerrit at coreboot.org
Fri Oct 12 17:15:13 CEST 2018
Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/29011 )
Change subject: amd/stoneyridge: Clarify XHCI_PM register definitions
......................................................................
amd/stoneyridge: Clarify XHCI_PM register definitions
Change-Id: I1b44ffd7c0244b0408c3823d634a9b8d5038462f
Signed-off-by: Marshall Dawson <marshalldawson3rd at gmail.com>
Reviewed-on: https://review.coreboot.org/29011
Tested-by: build bot (Jenkins) <no-reply at coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel at silverbackltd.com>
---
M src/soc/amd/stoneyridge/include/soc/southbridge.h
1 file changed, 16 insertions(+), 17 deletions(-)
Approvals:
build bot (Jenkins): Verified
Richard Spiegel: Looks good to me, approved
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index d4af8a1..ce3660b 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -279,27 +279,26 @@
#define PWR_RESET_CFG 0x10
#define TOGGLE_ALL_PWR_GOOD BIT(1)
+/* XHCI_PM Registers: 0xfed81c00 */
#define XHCI_PM_INDIRECT_INDEX 0x48
#define XHCI_PM_INDIRECT_DATA 0x4c
#define XHCI_OVER_CURRENT_CONTROL 0x30
+#define USB_OC0 0
+#define USB_OC1 1
+#define USB_OC2 2
+#define USB_OC3 3
+#define USB_OC4 4
+#define USB_OC5 5
+#define USB_OC6 6
+#define USB_OC7 7
+#define USB_OC_DISABLE 0xf
+#define USB_OC_DISABLE_ALL 0xffff
+#define OC_PORT0_SHIFT 0
+#define OC_PORT1_SHIFT 4
+#define OC_PORT2_SHIFT 8
+#define OC_PORT3_SHIFT 12
+
#define EHCI_OVER_CURRENT_CONTROL 0x70
-
-#define USB_OC0 0
-#define USB_OC1 1
-#define USB_OC2 2
-#define USB_OC3 3
-#define USB_OC4 4
-#define USB_OC5 5
-#define USB_OC6 6
-#define USB_OC7 7
-#define USB_OC_DISABLE 0xf
-#define USB_OC_DISABLE_ALL 0xffff
-
-#define OC_PORT0_SHIFT 0
-#define OC_PORT1_SHIFT 4
-#define OC_PORT2_SHIFT 8
-#define OC_PORT3_SHIFT 12
-
#define EHCI_HUB_CONFIG4 0x90
#define DEBUG_PORT_SELECT_SHIFT 16
#define DEBUG_PORT_ENABLE BIT(18)
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I1b44ffd7c0244b0408c3823d634a9b8d5038462f
Gerrit-Change-Number: 29011
Gerrit-PatchSet: 2
Gerrit-Owner: Marshall Dawson <marshalldawson3rd at gmail.com>
Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd at gmail.com>
Gerrit-Reviewer: Martin Roth <martinroth at google.com>
Gerrit-Reviewer: Richard Spiegel <richard.spiegel at silverbackltd.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
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