[coreboot-gerrit] Change in coreboot[master]: riscv: add support to block smp in each stage

[Xiang Wang (Code Review)]

Hello Shawn Chang, Jonathan Neuschäfer, build bot (Jenkins), Philipp Hug, 

I'd like you to reexamine a change. Please visit

    https://review.coreboot.org/29024

to look at the new patch set (#4).

Change subject: riscv: add support to block smp in each stage
......................................................................

riscv: add support to block smp in each stage

Change-Id: I8d508c3d0f65a022010e74f8edad7ad2cfdc7dee
Signed-off-by: Xiang Wang <wxjstz at 126.com>
---
M src/arch/riscv/boot.c
M src/arch/riscv/bootblock.S
M src/arch/riscv/ramstage.S
M src/arch/riscv/stages.c
M src/soc/sifive/fu540/Kconfig
M src/soc/sifive/fu540/Makefile.inc
6 files changed, 19 insertions(+), 9 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/29024/4
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I8d508c3d0f65a022010e74f8edad7ad2cfdc7dee
Gerrit-Change-Number: 29024
Gerrit-PatchSet: 4
Gerrit-Owner: Xiang Wang <wxjstz at 126.com>
Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
Gerrit-Reviewer: Philipp Hug <philipp at hug.cx>
Gerrit-Reviewer: Shawn Chang <citypw at gmail.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
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