[coreboot-gerrit] Change in coreboot[master]: sb/amd/cimx/sb[89]00: Use CF9 reset

[Nico Huber (Code Review)]

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/29056


Change subject: sb/amd/cimx/sb[89]00: Use CF9 reset
......................................................................

sb/amd/cimx/sb[89]00: Use CF9 reset

Change-Id: I2d277b0845b4e8977b68892c2e5e00d8918e063f
Signed-off-by: Nico Huber <nico.h at gmx.de>
---
M src/northbridge/amd/agesa/family14/state_machine.c
M src/southbridge/amd/cimx/sb800/Kconfig
M src/southbridge/amd/cimx/sb800/reset.c
M src/southbridge/amd/cimx/sb900/Kconfig
M src/southbridge/amd/cimx/sb900/reset.c
5 files changed, 10 insertions(+), 42 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/29056/1

diff --git a/src/northbridge/amd/agesa/family14/state_machine.c b/src/northbridge/amd/agesa/family14/state_machine.c
index fd9e3d0..81ce57f 100644
--- a/src/northbridge/amd/agesa/family14/state_machine.c
+++ b/src/northbridge/amd/agesa/family14/state_machine.c
@@ -18,11 +18,11 @@
 
 #include <arch/io.h>
 #include <cbmem.h>
+#include <cf9_reset.h>
 #include <device/device.h>
 #include <device/pci_def.h>
 #include <device/pci_ops.h>
 #include <halt.h>
-#include <reset.h>
 #include <smp/node.h>
 #include <northbridge/amd/agesa/state_machine.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
@@ -46,7 +46,7 @@
 		u32 mct_cfg_lo = pci_read_config32(dev, 0x118);
 		if (mct_cfg_lo & (1<<19)) {
 			printk(BIOS_CRIT, "C6DramLock is set, resetting\n");
-			hard_reset();
+			system_reset();
 		}
 	}
 }
diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig
index 07232f1..aa5160b 100644
--- a/src/southbridge/amd/cimx/sb800/Kconfig
+++ b/src/southbridge/amd/cimx/sb800/Kconfig
@@ -19,7 +19,8 @@
 	select IOAPIC
 	select HAVE_USBDEBUG_OPTIONS
 	select AMD_SB_CIMX
-	select HAVE_HARD_RESET
+	select HAVE_CF9_RESET
+	select HAVE_CF9_RESET_PREPARE
 
 if SOUTHBRIDGE_AMD_CIMX_SB800
 config BOOTBLOCK_SOUTHBRIDGE_INIT
diff --git a/src/southbridge/amd/cimx/sb800/reset.c b/src/southbridge/amd/cimx/sb800/reset.c
index 40e861c..883ac3e 100644
--- a/src/southbridge/amd/cimx/sb800/reset.c
+++ b/src/southbridge/amd/cimx/sb800/reset.c
@@ -17,14 +17,14 @@
 #define __SIMPLE_DEVICE__
 
 #include <arch/io.h>
-#include <reset.h>
+#include <cf9_reset.h>
 
 #define HT_INIT_CONTROL		0x6C
 #define HTIC_BIOSR_Detect	(1<<5)
 
 #define NODE_PCI(x, fn)	(((CONFIG_CDB+x)<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
 
-static inline void set_bios_reset(void)
+void cf9_reset_prepare(void)
 {
 	u32 nodes;
 	u32 htic;
@@ -39,20 +39,3 @@
 		pci_write_config32(dev, HT_INIT_CONTROL, htic);
 	}
 }
-
-void do_hard_reset(void)
-{
-	set_bios_reset();
-	/* Try rebooting through port 0xcf9 */
-	/* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
-	outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);
-	outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
-}
-
-//SbReset();
-void do_soft_reset(void)
-{
-	set_bios_reset();
-	/* link reset */
-	outb(0x06, 0x0cf9);
-}
diff --git a/src/southbridge/amd/cimx/sb900/Kconfig b/src/southbridge/amd/cimx/sb900/Kconfig
index 1fab6a7..be3b16d 100644
--- a/src/southbridge/amd/cimx/sb900/Kconfig
+++ b/src/southbridge/amd/cimx/sb900/Kconfig
@@ -18,7 +18,8 @@
 	default n
 	select IOAPIC
 	select AMD_SB_CIMX
-	select HAVE_HARD_RESET
+	select HAVE_CF9_RESET
+	select HAVE_CF9_RESET_PREPARE
 
 if SOUTHBRIDGE_AMD_CIMX_SB900
 config SATA_CONTROLLER_MODE
diff --git a/src/southbridge/amd/cimx/sb900/reset.c b/src/southbridge/amd/cimx/sb900/reset.c
index 40e861c..883ac3e 100644
--- a/src/southbridge/amd/cimx/sb900/reset.c
+++ b/src/southbridge/amd/cimx/sb900/reset.c
@@ -17,14 +17,14 @@
 #define __SIMPLE_DEVICE__
 
 #include <arch/io.h>
-#include <reset.h>
+#include <cf9_reset.h>
 
 #define HT_INIT_CONTROL		0x6C
 #define HTIC_BIOSR_Detect	(1<<5)
 
 #define NODE_PCI(x, fn)	(((CONFIG_CDB+x)<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
 
-static inline void set_bios_reset(void)
+void cf9_reset_prepare(void)
 {
 	u32 nodes;
 	u32 htic;
@@ -39,20 +39,3 @@
 		pci_write_config32(dev, HT_INIT_CONTROL, htic);
 	}
 }
-
-void do_hard_reset(void)
-{
-	set_bios_reset();
-	/* Try rebooting through port 0xcf9 */
-	/* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
-	outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);
-	outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
-}
-
-//SbReset();
-void do_soft_reset(void)
-{
-	set_bios_reset();
-	/* link reset */
-	outb(0x06, 0x0cf9);
-}

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I2d277b0845b4e8977b68892c2e5e00d8918e063f
Gerrit-Change-Number: 29056
Gerrit-PatchSet: 1
Gerrit-Owner: Nico Huber <nico.h at gmx.de>
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