[coreboot-gerrit] Change in coreboot[master]: nb/i945: Check if IGD is enabled before R/W to dev(0, 2)

Elyes HAOUAS (Code Review) gerrit at coreboot.org
Fri Oct 5 14:45:30 CEST 2018


Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28935


Change subject: nb/i945: Check if IGD is enabled before R/W to dev(0, 2)
......................................................................

nb/i945: Check if IGD is enabled before R/W to dev(0, 2)

Change-Id: I51ab94393710ce0222b353ab0cef28621fafaacf
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/northbridge/intel/i945/raminit.c
1 file changed, 12 insertions(+), 6 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/28935/1

diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index c259530..e95dda0 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -2148,7 +2148,7 @@
 	u8 reg8;
 	u16 reg16;
 	u32 reg32;
-	int integrated_graphics = 1;
+	int integrated_graphics = 0;
 	int i;
 
 	reg32 = MCHBAR32(C0DRT2);
@@ -2292,9 +2292,13 @@
 	reg8 |= (1 << 4);
 	pci_write_config8(PCI_DEV(0, 0x0, 0), 0xfc, reg8);
 
-	reg8 = pci_read_config8(PCI_DEV(0, 0x2, 0), 0xc1);
-	reg8 |= (1 << 2);
-	pci_write_config8(PCI_DEV(0, 0x2, 0), 0xc1, reg8);
+	if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) &
+	    (DEVEN_D2F0 | DEVEN_D2F1)) {
+		integrated_graphics = 1;
+		reg8 = pci_read_config8(PCI_DEV(0, 0x2, 0), 0xc1);
+		reg8 |= (1 << 2);
+		pci_write_config8(PCI_DEV(0, 0x2, 0), 0xc1, reg8);
+	}
 
 #ifdef C2_SELF_REFRESH_DISABLE
 
@@ -2755,10 +2759,12 @@
 	 * Program Graphics Frequency
 	 * Set core display and render clock on 945GC to the max
 	 */
-	if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM))
+	if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) {
 		sdram_program_graphics_frequency(&sysinfo);
-	else
+	} else if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) &
+			(DEVEN_D2F0 | DEVEN_D2F1)) {
 		pci_write_config16(PCI_DEV(0, 2, 0), GCFC, 0x0534);
+	}
 
 	/* Program System Memory Frequency */
 	sdram_program_memory_frequency(&sysinfo);

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I51ab94393710ce0222b353ab0cef28621fafaacf
Gerrit-Change-Number: 28935
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
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